Semiconductor device and method of manufacture thereof

ABSTRACT

Semiconductor chips ( 4 ), ( 5 ) are bonded and fixed to each other in a state where the rear surfaces of the respective semiconductor chips are faced to each other so that the other longer latus ( 4 A 2 ) of the semiconductor chip ( 4 ) and one longer latus ( 5 A 1 ) of the semiconductor chip ( 5 ) may confront the side of leads ( 10 B), and supporting leads ( 8 ) are bonded and fixed onto the circuit forming surface ( 4 A) of the semiconductor chip ( 4 ) or the circuit forming surface ( 5 A) of the semiconductor chip ( 5 ). Owing to such a construction, the structure of a semiconductor device can be thinned. 
     The semiconductor chips ( 4 ), ( 5 ) are bonded and fixed to each other in a state where the, positions of the respective semiconductor chips are staggered relatively to each other so that the electrodes ( 6 ) of the semiconductor chip ( 4 ) may lie outside the other longer latus ( 5 A 2 ) of the semiconductor chip ( 5 ), and that the electrodes ( 6 ) of the semiconductor chip ( 5 ) may lie outside the other longer latus ( 4 A 2 ) of the semiconductor chip ( 4 ). Owing to such a construction, the available percentage of the products of the semiconductor device can be heightened.

TECHNICAL FIELD

The present invention relates to a semiconductor device, and moreparticularly to techniques which are effective when applied to asemiconductor device wherein two semiconductor chips are stacked andthen encapsulated with an one resin body.

BACKGROUND ART

In order to enlarge the capacity of a storage circuit system, there hasbeen proposed a stacked type semiconductor device wherein twosemiconductor chips, in each of which a storage circuit subsystem isconstructed, are stacked and then encapsulated with an one resin body.By way of example, a stacked type semiconductor device of LOC (Lead OnChip) structure is disclosed in the official gazette of Japanese PatentLaid-Open No. 58281/1995. Besides, a stacked type semiconductor deviceof tab structure is disclosed in the official gazette of Japanese PatentLaid-Open No. 302165/1992.

The stacked type semiconductor device of LOC structure is constructedhaving a first semiconductor chip and a second semiconductor chip ineach of which a plurality of electrodes are formed on a circuit formingsurface being the front surface (one principal surface) of front andrear surfaces (one principal surface and the other principal surfaceopposing to each other); a plurality of first leads which are bonded andfixed to the circuit forming surface of the first semiconductor chipthrough an insulating film, and which are electrically connected to theelectrodes of this circuit forming surface through pieces of conductivewire; a plurality of second leads which are bonded and fixed to thecircuit forming surface of the second semiconductor chip through aninsulating film, and which are electrically connected to the electrodesof this circuit forming surface through pieces of conductive wire; and aresin body which encapsulates the first semiconductor chip, the secondsemiconductor chip, the inner portions of the first leads, the innerportions of the second leads, and the wire pieces. The firstsemiconductor chip and the second semiconductor chip are stacked to eachother in a state where their circuit forming surfaces are held inopposition to each other. The first leads and the second leads areindividually joined in a state where their connection portions areplaced one over the other.

The stacked type semiconductor device of tab structure is constructedhaving a first semiconductor chip which is fixed to the front surface(one principal surface) of the front and rear surfaces (one principalsurface and the other principal surface opposing to each other) of a tab(also termed “die pad”) through an adhesive layer; a secondsemiconductor chip which is fixed to the rear surface (the otherprincipal surface) of the tab through an adhesive layer; a plurality ofdedicated leads which are electrically connected to the electrodes ofeither of the first or second semiconductor chips through pieces ofconductive wire; a plurality of common leads which are electricallyconnected to the electrodes of both of the first and secondsemiconductor chips through pieces of conductive wire; and a resin bodywhich encapsulates the first semiconductor chip, the secondsemiconductor chip, the inner portions of the dedicated leads, the innerportions of the common leads, and the wire pieces. The electrodes ofeach of the first and second semiconductor chips are formed on the twolonger latus sides of the circuit forming surface opposing to each otherand along the respective longer latera thereof. The dedicated leads andthe common leads are respectively arranged outside the two longer lateraof each of the corresponding semiconductor chips.

Before developing a stacked type semiconductor device, the inventorsenvisaged problems stated below.

With the LOC structure, the semiconductor device is manufactured usingtwo lead frames, and hence, the fabrication cost thereof becomes high.On the other hand, with the tab structure, the semiconductor device canbe manufactured using a single lead frame. Since, however, thesemiconductor chips of mirror inversion circuit patterns need to beemployed, the fabrication cost of the semiconductor device becomes higheven with the tab structure. More specifically, with the tab structure,the two semiconductor chips are respectively mounted on the front andrear surfaces of the tab with their rear surfaces facing each other.Therefore, in the case where the electrodes are formed on the sides ofthe two longer latera of each circuit forming surface opposing to eachother, the electrodes of the lower semiconductor chip are reversed onthe right and left sides to those of the upper semiconductor chip.

In this regard, the semiconductor chips of the mirror inversion circuitpatterns are dispensed with by employing two semiconductor chips each ofwhich is formed with electrodes on one latus side, and by mounting thetwo semiconductor chips on the front and rear surfaces of a tab so thatone latus side of one semiconductor chip may be located on the oppositeside of the other semiconductor chip to one latus side thereof. It istherefore possible to achieve curtailment in the fabrication cost of thesemiconductor device of the tab structure.

With the tab structure, however, the thickness of the resin bodyenlarges, and it is difficult to construct the stacked typesemiconductor device as a TSOP (Thin Small Outline Package) type whoseresin body is 1.0˜1.1 [mm] thick. More specifically, since the tabstructure constructs the semiconductor device by mounting thesemiconductor chips on the front and rear surfaces of the tab, the tabexists between the upper semiconductor chip and the lower semiconductorchip, and a distance from the circuit forming surface of the uppersemiconductor chip to that of the lower semiconductor chip increases, sothat the resin body thickens. Further, on account of the construction inwhich the semiconductor chips are mounted on the front and rear surfacesof the tab, two adhesive layers exist between the upper semiconductorchip and the lower semiconductor chip, and the distance from the circuitforming surface of the upper semiconductor chip to that of the lowersemiconductor chip increases, so that the resin body thickens. Theinventors study has revealed that the thickness of the resin body can beset at 1.0˜1.1 [mm] or less by thinning each semiconductor chip down to0.1725˜0.2 [mm]. In such a case, however, the mechanical strength of thesemiconductor chip lowers, and hence, drawbacks such as cracks andfractures are liable to occur in the semiconductor chip. The drawbacksoften occur especially at the dicing step of fabrication for splitting asemiconductor wafer into a plurality of chips, and at the die bondingstep of fabrication for mounting the semiconductor chips on the tab.

Besides, with the tab structure, inferior connections are liable tooccur between the electrodes of the semiconductor chips and the wirepieces. More specifically, it is difficult to bring the tab into touchwith a heat stage after the semiconductor chips have been mounted on thefront and rear surfaces of the tab. Therefore, the heat of the heatstage is not effectively conducted, and the inferior connections betweenthe electrodes of the semiconductor chips and the wire pieces are liableto occur.

An object of the present invention is to provide a technique capable ofattaining the thinned construction of a semiconductor device wherein twosemiconductor chips are stacked and then encapsulated with an one resinbody.

Another object of the present invention is to provide a techniquecapable of heightening the available percentage of the products of thethinned semiconductor device.

The above and other objects and novel features of the present inventionwill become apparent from the description of this specification whenread in conjunction with the accompanying drawings.

DISCLOSURE OF THE INVENTION

Typical aspects of performance out of the present invention disclosed inthis application are briefly summarized as follows:

(1) A semiconductor device comprising a resin body; a firstsemiconductor chip and a second semiconductor chip which lie within saidresin body, each of which is formed in a square shape when viewed inplan, and each of which is formed with a plurality of electrodes on aside of a first latus of a front surface of front and rear surfacesthereof and along the first latus; a plurality of first leads whichextend inside and outside said resin body, which are arranged outsidesaid first latus of said first semiconductor chip, and which areelectrically connected to the corresponding electrodes of said firstsemiconductor chip through pieces of conductive wire; a plurality ofsecond leads which extend inside and outside said resin body, which arearranged outside a second latus of said first semiconductor chipopposing to said first latus thereof, and which are electricallyconnected to the corresponding electrodes of said second semiconductorchip through pieces of conductive wire; and supporting leads whichsupport said first semiconductor chip and said second semiconductorchip;

wherein said first semiconductor chip and said second semiconductor chipare bonded and fixed to each other in a state where the rear surfaces ofthe respective semiconductor chips are faced to each other so that thesecond latus of said first semiconductor chip and said first latus ofsaid second semiconductor chip may confront a side of said second leads;and

said supporting leads are bonded and fixed to the front surface of saidfirst semiconductor chip or the front surface of said secondsemiconductor chip.

(2) A semiconductor device as defined in the means (1), wherein saidfirst semiconductor chip and said second semiconductor chip are bondedand fixed in a state where positions of the respective semiconductorchips are staggered relatively to each other so that said electrodes ofsaid first semiconductor chip may lie outside a second latus of saidsecond semiconductor chip opposing to said first latus thereof, and thatsaid electrodes of said second semiconductor chip may lie outside saidsecond latus of said first semiconductor chip.

(3) A semiconductor device as defined in the means (2), wherein saidfirst semiconductor chip and said second semiconductor chip are bondedand fixed in a state where the positions of the respective semiconductorchips are staggered relatively to each other so that a third latus ofsaid first semiconductor chip intersecting with said first latus thereofmay lie outside a third latus of said second semiconductor chipintersecting with said first latus thereof and lying on the same side asthe third latus of said first semiconductor chip, and that a fourthlatus of said second semiconductor chip opposing to the third latusthereof may lie outside a fourth latus of said first semiconductor chipopposing to said third latus thereof and lying on the same side as thefourth latus of said second semiconductor chip.

According to the:means (1) explained above, any tab does not existbetween the semiconductor chip and the semiconductor chip, so that adistance from the front surface of the first semiconductor chip to thefront surface of the second semiconductor chip can be shortened.Moreover, since only one adhesive layer exists between the firstsemiconductor chip and the second semiconductor chip, the distance fromthe front surface of the first semiconductor chip to the front surfaceof the second semiconductor chip can be shortened. Furthermore, sincethe supporting leads are bonded and fixed to the front surface of thefirst semiconductor chip or that of the second semiconductor chip, thethickness of each of the supporting leads is cancelled by the loopheight of the wire pieces, and the thickness of the resin body is notaffected by the supporting leads. As a result, the resin body can bethinned, and hence, the thinned structure of the semiconductor devicecan be achieved.

According to the means (2) explained above, at a wire bonding step, theregion of the rear surface of the first semiconductor chip opposing tothe electrodes thereof can be held in direct touch with a heat stage,and the heat of the heat stage is effectively conducted to theelectrodes of the first semiconductor chip, so that the inferiorconnections between the electrodes of the first semiconductor chip andthe wire pieces can be relieved. In addition, the region of the rearsurface of the second semiconductor chip opposing to the electrodesthereof can be held in direct touch with a heat stage, and the heat ofthe heat stage is effectively conducted to the electrodes of the secondsemiconductor chip, so that the inferior connections between theelectrodes of the first semiconductor chip and the wire pieces can berelieved. As a result, the available percentage of the products of thesemiconductor device can be heightened.

According to the means (3) explained above, at the wire bonding step,the area of touch between the rear surface of the first semiconductorchip and the heat stage increases, and hence, a time period for heatingthe second semiconductor chip at this step can be shortened. Also, thearea of touch between the rear surface of the second semiconductor chipand the heat stage increases, and hence, a time period for heating thesecond semiconductor chip can be shortened at the wire bonding step. Asa result, the production efficiency of the semiconductor device can beheightened.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a plan view of a semiconductor device being Embodiment of thepresent invention in a state where the upper part of a resin body hasbeen removed.

FIG. 2 is a bottom view of the semiconductor device being Embodiment 1of the present invention in a state where the lower part of the resinbody has been removed.

FIG. 3 is a sectional view taken along line A—A indicated in FIG. 1.

FIG. 4 is a sectional view taken along line B—B indicated in FIG. 1.

FIG. 5 is a plan view of a lead frame which is used in a manufacturingprocess for the semiconductor device being Embodiment 1 of the presentinvention.

FIG. 6 is a sectional view for explaining the manufacture of thesemiconductor device being Embodiment 1 of the present invention.

FIG. 7 is a sectional view for explaining the manufacture of thesemiconductor device being Embodiment 1 of the present invention.

FIG. 8 is a sectional view for explaining the manufacture of thesemiconductor device being Embodiment 1 of the present invention.

FIG. 9 is a sectional view for explaining the manufacture of thesemiconductor device being Embodiment 1 of the present invention.

FIG. 10 is a sectional view of essential portions in a state where thesemiconductor device being Embodiment 1 of the present invention ispackaged on a mounting substrate.

FIG. 11 is a plan view of a semiconductor device being Embodiment 2 ofthe present invention in a state where the upper part of a resin bodyhas been removed.

FIG. 12 is a sectional view taken along line C—C indicated in FIG. 11.

FIG. 13 is a sectional view taken along line D—D indicated in FIG. 11.

FIG. 14 is a plan view of a lead frame which is used in a manufacturingprocess for the semiconductor device being Embodiment 2 of the presentinvention.

FIG. 15 is a plan view of a semiconductor device being Embodiment 3 ofthe present invention in a state where the upper part of a resin bodyhas been removed.

FIG. 16 is a sectional view taken along line E—E indicated in FIG. 15.

FIG. 17 is a plan view of a lead frame which is used in a manufacturingprocess for the semiconductor device being Embodiment 3 of the presentinvention.

FIG. 18 is a plan view of a semiconductor device being Embodiment 4 ofthe present invention in a state where the upper part of a resin bodyhas been removed.

FIG. 19 is a sectional view of the semiconductor device being Embodiment4 of the present invention.

FIG. 20 is a plan view of a lead frame which is used in a manufacturingprocess for the semiconductor device being Embodiment 4 of the presentinvention.

FIG. 21 is a sectional view for explaining the manufacture of thesemiconductor device being Embodiment 4 of the present invention.

FIG. 22 is a sectional view for explaining the manufacture of thesemiconductor device being Embodiment 4 of the present invention.

FIG. 23 is a sectional view for explaining the manufacture of thesemiconductor device being Embodiment 4 of the present invention.

FIG. 24 is a sectional view for explaining the manufacture of thesemiconductor device being Embodiment 4 of the present invention.

FIG. 25 is a sectional view for explaining the manufacture of thesemiconductor device being Embodiment 4 of the present invention.

FIG. 26 is a schematic view for explaining the manufacture of thesemiconductor device being Embodiment 4 of the present invention.

FIG. 27 is a schematic view for explaining the manufacture of thesemiconductor device being Embodiment 4 of the present invention.

FIG. 28 is a schematic view for explaining the manufacture of thesemiconductor device being Embodiment 4 of the present invention.

FIG. 29 is a schematic view for explaining the manufacture of thesemiconductor device being Embodiment 4 of the present invention.

FIG. 30 is a plan view of a semiconductor device being Embodiment 5 ofthe present invention in a state where the upper part of a resin bodyhas been removed.

FIG. 31 is a sectional view of the semiconductor device being Embodiment5 of the present invention.

FIG. 32 is a sectional view of a semiconductor device showing amodification to Embodiment 5 of the present invention.

FIG. 33 is a sectional view of a semiconductor device being Embodiment 6of the present invention.

FIG. 34 is a sectional view of a semiconductor device showing amodification to Embodiment 6 of the present invention.

FIG. 35 is a plan view of a semiconductor device being Embodiment 7 ofthe present invention in a state here the upper part of a resin body hasbeen removed.

FIG. 36 is a sectional view of the semiconductor device being Embodiment7 of the present invention.

FIG. 37 is a sectional view of a semiconductor device showing amodification to Embodiment 7 of the present invention.

FIG. 38 is a plan view of a semiconductor device being Embodiment 8 ofthe present invention in a state where the upper part of a resin bodyhas been removed.

FIG. 39 is a sectional view of the semiconductor device being Embodiment8 of the present invention.

FIG. 40 is a sectional view of a semiconductor device showing amodification to Embodiment 8 of the present invention.

FIG. 41 is a plan view of a semiconductor device being Embodiment 9 ofthe present invention in a state where the upper part of a resin bodyhas been removed.

FIG. 42 is a sectional view of the semiconductor device being Embodiment9 of the present invention.

FIG. 43 is a sectional view of a semiconductor device being Embodiment10 of the present invention.

FIG. 44 is a sectional view of a semiconductor device being Embodiment11 of the present invention.

FIG. 45 is a sectional view of a semiconductor device being Embodiment12 of the present invention.

FIG. 46 is a sectional view of a semiconductor device being Embodiment13 of the present invention.

FIG. 47 is a sectional view of a semiconductor device being Embodiment14 of the present invention.

FIG. 48 is a plan view of semiconductor chips which are assembled in thesemiconductor device being Embodiment 14 of the present invention.

BEST MODES FOR CARRYING OUT THE INVENTION

Now, embodiments of the present invention will be described in detailwith reference to the drawings. Incidentally, throughout the drawingsfor describing the embodiments, the same symbols are assigned to partshaving the same functions, which shall be omitted from repeatedexplanation.

EMBODIMENT 1

In this embodiment, there will be described an example in which thepresent invention is applied to a semiconductor device of TSOP typebeing a bidirectional lead array structure.

FIG. 1 is a plan view of a semiconductor device being Embodiment 1 ofthe present invention in a state where the upper part of a resin bodyhas been removed, FIG. 2 is a bottom view of the semiconductor device ina state where the lower part of the resin body has been removed, FIG. 3is a sectional view taken along line A—A indicated in FIG. 1, and FIG. 4is a sectional view taken along line B—B indicated in FIG. 1. By theway, in FIGS. 1 and 2, a group of leads on the left side shown in FIG. 1correspond to a group of leads on the right side shown in FIG. 2, whilea group of leads on the right side shown in FIG. 1 correspond to a groupof leads on the left side shown in FIG. 2.

As illustrated in FIGS. 1, 2 and 3, the semiconductor device 1 of thisembodiment is so constructed that a semiconductor chip 4 and asemiconductor chip 5 are stacked one over the other, and that thesemiconductor chips 4 and 5 are encapsulated with the one resin body 12.The semiconductor chips 4, 5 are stacked in a state where the rearsurfaces (the other principal surfaces) of the front and rear surfacesof these semiconductor chips (each of which has one principal surfaceand the other principal surface opposing to each other) are faced toeach other.

Both the semiconductor chips 4, 5 are formed in the same geometries.Besides, the planar shape of each of the semiconductor chips 4, 5 is asquare shape, which is, for example, a rectangle in this embodiment.

By way of example, each of the semiconductor chips 4, 5 chiefly includesa semiconductor substrate which is made of single-crystal silicon, andmultiple wiring layers which are formed on the semiconductor substrate.An EEPROM (Electrically Erasable Programmable Read Only Memory) of 64[Mbits] called “flash memory”, for example, is constructed as a storagecircuit subsystem in each of the semiconductor chips 4, 5.

In a circuit forming surface 4A which is the front surface (oneprincipal surface) of the front and rear surfaces (one principal surfaceand the other principal surface opposing to each other) of thesemiconductor chip 4, a plurality of electrodes (bonding pads) 6 areformed on the side of one longer latus 4A1 of the two longer latera ofthis surface 4A opposing to each other and along this longer latus 4A1(refer to FIG. 1 and FIG. 3). The plurality of electrodes 6 arerespectively formed in the uppermost one of the multiple wiring layersof the semiconductor chip 4. The uppermost wiring layer is covered witha front surface protection film (final protection film) which is formedoverlying this wiring layer, and which is formed with bonding openingsfor denuding the front surfaces of the electrodes 6.

In a circuit forming surface 5A which is the front surface (oneprincipal surface) of the front and rear surfaces (one principal surfaceand the other principal surface opposing to each other) of thesemiconductor chip 5, a plurality of electrodes 6 are formed on the sideof one longer latus 5A1 of the two longer latera of this surface 5Aopposing to each other and along this longer latus 5A1 (refer to FIG. 2and FIG. 3). The plurality of electrodes 6 are respectively formed inthe uppermost one of the multiple wiring layers of the semiconductorchip 5. The uppermost wiring layer is covered with a front surfaceprotection film (final protection film) which is formed overlying thiswiring layer, and which is formed with bonding openings for denuding thefront surfaces of the electrodes 6.

The circuit pattern of the flash memory constructed in the semiconductorchip 4 is the same as that of the flash memory constructed in thesemiconductor chip 5. Besides, the arrangement pattern of the electrodes6 formed on the circuit forming surface 4A of the semiconductor chip 4is the same as that of the electrodes 6 formed on the circuit formingsurface 5A of the semiconductor chip 5. That is, the semiconductor chip4 and the semiconductor chip 5 are constructed with the same structureseach other.

The planar shape of the resin body 12 is a square shape, which is, forexample, a rectangle in this embodiment. A plurality of leads 10A arearrayed on the side of one longer latus of the two longer latera of theresin body 12 opposing to each other and along this longer latus (onelonger latus), while a plurality of leads 10B are arrayed on the side ofthe other longer latus and along this longer latus (the other longerlatus). The plurality of leads 10A are extended inside and outside theresin body 12, they are arranged outside one longer latus 4A1 of thesemiconductor chip 4, and they are electrically connected to thecorresponding electrodes 6 of the semiconductor chip 4 through pieces ofconductive wire 11, respectively (refer to FIG. 1 and FIG. 3). Theplurality of leads 10B are extended inside and outside the resin body12, they are arranged outside the other longer latus 4A2 of thesemiconductor chip 4 opposing to one longer latus 4A1 thereof, and theyare electrically connected to the corresponding electrodes 6 of thesemiconductor chip 5 through pieces of conductive wire 11, respectively(refer to FIG. 2 and FIG. 3).

Terminal names are given to the plurality of leads 10A, 10B,respectively. A “VCC terminal” is a supply potential terminal whosepotential is fixed to a power supply potential (for example, 5 [V]).A“VSS terminal” is a reference potential terminal whose potential isfixed to a reference potential (for example, 0 [V]). An “I/O0 terminal”˜an “I/O7 terminal” are data input/output terminals. An “RES terminal” isa reset terminal. An “R/B terminal” is a ready/busy terminal. A “CDEterminal” is a command data enable terminal. An “OE terminal” is anoutput enable terminal. An “SC terminal” is a serial clock terminal. A“WE terminal” is a write enable terminal. A “CE terminal” is a chipenable terminal. An “NC terminal” is a no-connection terminal.

The semiconductor chips 4, 5 are bonded and fixed to each other throughan adhesive layer 7 in the state in which the rear surfaces of thesesemiconductor chips are faced to each other so that the other longerlatus 4A2 of the semiconductor chip 4 and one longer latus 5A1 of thesemiconductor chip 5 may confront (lie on) the side of the leads 10B. Inother words, the semiconductor chips 4, 5 are bonded. and fixed to eachother in the state in which the rear surfaces of these semiconductorchips are faced to each other so that the latera of the respectivesemiconductor chips with the electrodes 6 arrayed thereon may lie on theopposite sides. In addition, both the semiconductor chips 4, 5 aresupported by supporting leads 8. The supporting leads 8 are bonded andfixed to the circuit forming surface 4A of the semiconductor chip 4through an adhesive layer 9.

For these reasons, any tab does not exist between the semiconductor chip4 and the semiconductor chip 5, so that a distance from the circuitforming surface 4A of the semiconductor chip 4 to the circuit formingsurface 5A of the semiconductor chip 5 can be shortened. Moreover, sinceonly the single adhesive layer 7 exists between the semiconductor chip 4and the semiconductor chip 5, the distance from the circuit formingsurface 4A of the semiconductor chip 4 to the circuit forming surface 5Aof the semiconductor chip 5 can be shortened. Furthermore, since thesupporting leads 8 are bonded and fixed to the circuit forming surface4A of the semiconductor chip 4, the thickness of each of the supportingleads 8 is cancelled by the loop height of the wire pieces 11 forelectrically connecting the electrodes 6 of the semiconductor chip 4with the leads 10A, and the thickness of the resin body 12 is notaffected by the supporting leads 8.

The semiconductor chips 4, 5 are bonded and fixed in a state where thepositions of these semiconductor chips are staggered relatively to eachother so that the electrodes 6 of the semiconductor chip 4 may lieoutside the other longer latus 5A2 of the semiconductor chip 5 opposingto one longer latus 5A1 thereof, and that the electrodes 6 of thesemiconductor chip 5 may lie outside the other longer latus 4A2 of thesemiconductor chip 4. In other words, the semiconductor chips 4 and 5are bonded and fixed in a state where the positions of thesesemiconductor chips are relatively shifted in a direction orthogonal tothe direction of arraying the electrodes 6.

Each of the leads 10A and the leads 10B includes an inner portion (innerlead portion) which is encapsulated with the resin body 12, and an outerportion (outer lead portion) which is led outside the resin body 12. Theouter portions are molded into, for example, a gull-wing shape as a flatmounting shape.

Gold (Au) wire, for example, is employed as the conductive wire 11. Byway of example, bonding in which ultrasonic vibrations are usedconjointly with thermocompression is employed as a method of connectingthe wire 11.

In order to attain a lower stress, the resin body 12 is formed of, forexample, a biphenyl-based resin which is doped with a phenolic hardener,silicone rubber, a filler, or the like. The resin body 12 is formed bytransfer molding which is well suited for mass production. The transfermolding is a method wherein, using a metal mold which includes a pot, arunner, a pouring gate and a cavity, a resin is injected under pressurefrom the pot into the cavity through the runner as well as the pouringgate, thereby to form a resin body.

Referring to FIG. 3, the thickness of each of the semiconductor chips 4,5 is 0.24 [mm], the thickness of the adhesive layer 7 is 0.01 [mm], thethickness of each of the leads 10A and leads 10B is 0.125 [mm], theheight (loop height) from the circuit forming surface 4A of thesemiconductor chip 4 to the top of the wire 11 for electricallyconnecting the electrodes 6 of this semiconductor chip 4 with the leads10A is 0.19 [mm], an interval from the top of the wire 11 to the uppersurface of the resin body 12 is 0.065 [mm], the thickness of the resinbody 11 is 1.0 [mm], and a height from the upper surface of the resinbody 12 to the mounting surface of the leads (10A, 10B) is 1.20 [mm].Incidentally, although not shown in the figure, a height from thecircuit forming surface 5A of the semiconductor chip 5 to the top of thewire 11 for electrically connecting the electrodes 6 of thissemiconductor chip 5 with the leads 10B is 0.19 [mm], and an intervalfrom the top of the wire 11 to the lower surface of the resin body 11 is0.065 [mm].

The upper surface of each of the supporting leads (suspension leads) 8is lower than the top of the wire 11. As shown in FIG. 4, the supportingleads 8 extend so as to traverse the two shorter latera 4A3 and 4A4 ofthe semiconductor chip 4 opposing to each other. By the way, in FIG. 4,symbol 5A3 denotes one of the two shorter latera of the semiconductorchip 5 opposing to each other, and symbol 5A4 denotes the other shorterlatus.

Next, a lead frame for use in a process for manufacturing thesemiconductor device 1 will be described with reference to FIG. 5. FIG.5 is a plan view of the lead frame. Incidentally, actual lead frameshave a multiple string structure so that a plurality of semiconductordevices can be manufactured. For the brevity of illustration, however,FIG. 5 shows one domain where one semiconductor device is manufactured.

As shown in FIG. 5, the lead frame LF1 is so constructed that aplurality of leads 10A, a plurality of leads 10B, supporting leads 8,etc. are arranged within a region which is defined by a frame member 14.The plurality of leads 10A are arrayed along one of the two longer latusparts of the frame member 14 opposing to each other, and are unitarywith the longer latus part. The plurality of leads 10B are arrayed alongthe other of the two longer latus parts of the frame member 14 opposingto each other, and are unitary with the other longer latus part. Thesupporting leads 8 are arranged between a group of leads consisting ofthe plurality of leads 10A and a group of leads consisting of theplurality of leads 10B, and are unitary with the frame member 14. Thatis, the lead frame LF1 has a bidirectional lead array structure.

Each of the plurality of leads 10A includes an inner portion which isencapsulated with the resin body, and an outer portion which is ledoutside the resin body. The inner portions and the outer portions arecoupled with each other through a tie bar 13. Likewise, each of theplurality of leads 10B includes an inner portion which is encapsulatedwith the resin body, and an outer portion which is led outside the resinbody. The inner portions and the outer portions are coupled with eachother through a tie bar 13.

By way of example, the lead frame LF1 is fabricated in such a way that aflat material, which is made of an iron (Fe)—nickel (Ni) alloy, orcopper. (Cu) or a copper alloy, is subjected to an etching work or apress work so as to form a predetermined lead pattern.

Next, the process for manufacturing the semiconductor device 1 will bedescribed with reference to FIG. 6 thru FIG. 9 (sectional views).

First, one semiconductor chip 4 is bonded and fixed onto the lead frameLF1. As shown in FIG. 6, the fixation between the lead frame LF1 and thesemiconductor chip 4 is done in such a way that the semiconductor chip 4is set on a heat stage 20, that the circuit forming surface 4A of thesemiconductor chip 4 is thereafter coated with an adhesive made of, forexample, a thermosetting resin, thereby to form the adhesive layer 9,and that the supporting leads 8 are thereafter pressedly secured ontothe circuit forming surface 4A of the semiconductor chip 4 by a bondingtool 21.

Subsequently, the electrodes 6 of the semiconductor chip 4 and the leads10A are electrically connected by the conductive wire pieces 11. Asshown in FIG. 7, the connections between the electrodes 6 of thesemiconductor chip 4 and the leads 10A are done in a state where thesemiconductor chip 4 is set on a heat stage 22, and where the leads 10Aand leads 10B are thereafter pushed against the heat stage 22 by a framekeeping member 23. Gold (Au) wire, for example, is employed as the wire11. Besides, a method of connecting the wire 11 is, for example, bondingin which ultrasonic vibrations are used conjointly withthermocompression.

Subsequently, the semiconductor chip 5 is bonded and fixed to thesemiconductor chip 4. As shown in FIG. 8, the fixation between thesemiconductor chip 4 and the semiconductor chip 5 is done in such a waythat the semiconductor chip 4 is set on a heat stage 23 with its circuitforming surface 4A facing downwards, that the rear surface of thesemiconductor chip 4 is thereafter coated with an adhesive made of, forexample, a silver (Ag) paste material, thereby to form the adhesivelayer 7, and that the semiconductor chip 5 is thereafter secured ontothe rear surface of the semiconductor chip 4 with its rear surfacefacing downwards. On this occasion, the rear surfaces of the respectivesemiconductor chips 4 and 5 are faced and bonded and fixed to each otherin the state of specified orientation in which one longer latus 5A1 ofthe semiconductor chip 5 lies opposite to one longer latus 4A1 of thesemiconductor chip 4. Besides, the rear surfaces of the respectivesemiconductor chips 4 and 5 are faced and bonded and fixed to each otherin the state of staggered positions in which the electrodes 6 of thesemiconductor chip 4 lie outside the other longer latus 5A2 of thesemiconductor chip 5, and in which the electrodes 6 of the semiconductorchip 5 lie outside the other longer latus 4A2 of the semiconductor chip4. Incidentally, at this step, the semiconductor chip 4 is set on theheat stage 23 with its circuit forming surface 4A facing downwards, andhence, the heat stage 23 is provided with a recess 23A in order toprevent this heat stage 23 from coming into touch with the wire 11.

Subsequently, the electrodes 6 of the semiconductor chip 5 and the leads10B are electrically connected by the conductive wire pieces 11. Asshown in FIG. 9, the connections between the electrodes 6 of thesemiconductor chip 5 and the leads 10B are done in a state where thesemiconductor chips 4 and 5 are set on a heat stage 24 with the circuitforming surface 5A of the semiconductor chip 5 facing upwards, and wherethe leads 10A and leads 10B are thereafter pushed against the heat stage24 by a frame keeping member 25. Gold (Au) wire, for example, isemployed as the wire 11. Besides, a method of connecting the wire 11 is,for example, bonding in which ultrasonic vibrations are used conjointlywith thermocompression. At this step, the partial region of the rearsurface of the semiconductor chip 5 opposing to the electrodes 6 thereofis exposed. Therefore, the heat stage 24 is provided with a protrusion25B beforehand so as to come into touch with the exposed partial regionof the rear surface, whereby this partial region of the rear surfaceopposing to the electrodes 6 of the semiconductor chip 5 can be held indirect touch with the heat stage 24. More specifically, the rearsurfaces of the respective semiconductor chips 4 and 5 are bonded andfixed to each other in the state of staggered positions in which theelectrodes 6 of the semiconductor chip 4 lie outside the other longerlatus 5A2 of the semiconductor chip 5 and in which the electrodes 6 ofthe semiconductor chip 5 lie outside the other longer latus 4A2 of thesemiconductor chip 4, whereby the partial region of the rear surface ofthe semiconductor chip 5 opposing to the electrodes 6 thereof can beheld in direct touch with the heat stage 24, and the heat of the heatstage 24 can be effectively conducted to the electrodes 6 of thesemiconductor chip 5, so that the inferior connections between theelectrodes 6 of the semiconductor chip 5 and the wire pieces 11 can berelieved. Incidentally, at this step, the semiconductor chip 4 is set onthe heat stage 24 with its circuit forming surface 4A facing downwards,and hence, the heat stage 24 is provided with a recess 24A in order toprevent this heat stage 24 from coming into touch with the wire 11.

Subsequently, the semiconductor chip 4, the semiconductor chip 5, thesupporting leads 8, the inner portions of the leads 10A, the innerportions of the leads 10B, and the wire pieces 11 are encapsulated witha resin, thereby to form the resin body 12. The formation of the resinbody 12 is done by transfer molding.

Subsequently, the tie bar 13 coupled to the leads 10A and the tie bar 13coupled to the leads 10B are cut away, the outer portions of therespective leads 10A and 10B are thereafter subjected to a platingtreatment, the leads 10A and 10B are thereafter cut away from the framemember 14 of the lead frame LF1, the outer portions of the respectiveleads 10A and 10B are thereafter molded into, for example, a gull-wingshape as a flat mounting shape, and the supporting leads 8 arethereafter cut away from the frame member 14 of the lead frame LF1. Inthis way, the semiconductor device 1 shown in FIGS. 1, 2 and 3 issubstantially completed.

As shown in FIG. 10 (a sectional view of essential portions), aplurality of semiconductor devices 1 thus constructed are packaged on amounting substrate 30 as the constituent components of an electrondevice which constructs one circuit system. Since each semiconductordevice 1 has the leads of the same functions arranged in opposition,wiring lines 31 for electrically connecting the leads 10A with the leads10B can be rectilinearly laid. Moreover, wiring lines 31 forelectrically connecting the leads 10B of one semiconductor device 1 withthe leads 10A of another semiconductor device 1 can be rectilinearlylaid. Accordingly, the number of wiring layers of the mounting substrate30 can be decreased, and hence, the electron device, for example, amemory module can be structurally thinned.

As described above, the following effects are attained in accordancewith this embodiment:

(1) The semiconductor chip 4 and the semiconductor chip 5 are bonded andfixed to each other in the state in which the rear surfaces of thesesemiconductor chips are faced to each other so that the other longerlatus 4A2 of the semiconductor chip 4 and one longer latus 5A1 of thesemiconductor chip 5 may confront the side of the leads 10B, and thesupporting leads 8 are bonded and fixed to the circuit forming surface4A of the semiconductor chip 4.

For these reasons, any tab does not exist between the semiconductor chip4 and the semiconductor chip 5, so that a distance from the circuitforming surface 4A of the semiconductor chip 4 to the circuit formingsurface 5A of the semiconductor chip 5 can be shortened. Moreover, sinceonly one adhesive layer exists between the semiconductor chip 4 and thesemiconductor chip 5, the distance from the circuit forming surface 4Aof the semiconductor chip 4 to the circuit forming surface 5A of thesemiconductor chip 5 can be shortened. Furthermore, since the supportingleads 8 are bonded and fixed to the circuit forming surface 4A of thesemiconductor chip 4, the thickness of each of the supporting leads 8 iscancelled by the loop height of the wire pieces 11, and the thickness ofthe resin body 12 is not affected by the supporting leads 8. As aresult, the resin body 12 can be thinned, and hence, the thinnedstructure of the semiconductor device 1 can be achieved.

In addition, since the resin body 12 can be thinned without reducing thethickness of each of the semiconductor chips (4, 5), the thinnedsemiconductor device 1 of high available percentage can be offered.

Besides, since the resin body 12 can be thinned, the semiconductordevice 1 in which the two semiconductor chips (4, 5) are stacked andthen encapsulated with the one resin body 12 can be constructed as theTSOP type.

It is also dispensed with to use two lead frames or to use semiconductorchips of mirror inversion circuit patterns. It is therefore possible toachieve curtailment in the cost of the semiconductor device 1 andthinning in the structure thereof.

(2) The semiconductor chip 4 and the semiconductor chip 5 are bonded andfixed to each other in the state of staggered positions in which theelectrodes 6 of the semiconductor chip 4 lie outside the other longerlatus 5A2 of the semiconductor chip 5, and in which the electrodes 6 ofthe semiconductor chip 5 lie outside the other longer latus 4A2 of thesemiconductor chip 4.

For this reason, at the wire bonding step, the partial region of therear surface of the semiconductor chip 5 opposing to the electrodes 6thereof can be held in direct touch with the heat stage 24, and the heatof the heat stage 24 can be effectively conducted to the electrodes 6 ofthe semiconductor chip 5, so that the inferior connections between theelectrodes 6 of the semiconductor chip 5 and the wire pieces 11 can berelieved. As a result, the available percentage of the products of thesemiconductor device 1 in the manufacturing process (assembling process)can be heightened.

By the way, although the example in which the supporting leads 8 arebonded and fixed to the circuit forming surface 4A of the semiconductorchip 4 has been explained in this embodiment, the supporting leads 8 maywell be bonded and fixed to the circuit forming surface 5A of thesemiconductor chip 5. In this case, the supporting leads 8 are subjectedto a bending work for locating the chip fixation part of this supportingleads onto the side of the circuit forming surface 5A of thesemiconductor chip 5. Even in such a case, the thickness of each of thesupporting leads 8 is cancelled by the loop height of the wire pieces 11for electrically connecting the electrodes 6 of the semiconductor chip 5with the leads 10B, so that the thickness of the resin body 12 is notaffected by the supporting leads 8.

EMBODIMENT 2

FIG. 11 is a plan view of a semiconductor device being Embodiment 2 ofthe present invention in a state where the upper part of a resin bodyhas been removed, FIG. 12 is a sectional view taken along line C—Cindicated in FIG. 11, and FIG. 13 is a sectional view taken along lineD—D indicated in FIG. 11.

As illustrated in FIGS. 11, 12 and 13, the semiconductor device 2 ofthis embodiment has basically the same construction as that ofEmbodiment 1 described before, but it differs from the foregoingembodiment in constructional points explained below.

A semiconductor chip 4 and a semiconductor chip 5 are bonded and fixedin a state where the positions of these semiconductor chips arestaggered relatively to each other so that one shorter latus 4A3 of thesemiconductor chip 4 intersecting with one longer latus 4A1 thereof maylie outside one shorter latus 5A3 of the semiconductor chip 5intersecting with one longer latus 5A1 thereof and lying on the sameside as one shorter latus 4A3 of the semiconductor chip 4, and that theother shorter latus 5A4 of the semiconductor chip 5 opposing to oneshorter latus 5A3 thereof may lie outside the other shorter latus 4A4 ofthe semiconductor chip 4 opposing to one shorter latus 4A3 thereof andlying on the same side as the other shorter latus 5A4 of thesemiconductor chip 5. In other words, the semiconductor chips 4 and 5are bonded and fixed in a state where the positions of thesesemiconductor chips are relatively shifted in the direction of arrayingthe electrodes 6 thereof.

Besides, the semiconductor device 2 includes a supporting lead 8A whichis arranged outside one shorter latus 4A3 of the semiconductor chip 4and one shorter latus 5A3 of the semiconductor chip 5, and a supportinglead 8B which is arranged outside the other shorter latus 4A4 of thesemiconductor chip 4 and the other shorter latus 5A4 of thesemiconductor chip 5. The supporting lead 8A is bonded and fixed to therear surface of the semiconductor chip 4 through an adhesive layer 9,outside one shorter latus 5A3 of the semiconductor chip 5, while thesupporting lead 8B is bonded and fixed to the rear surface of thesemiconductor chip 5 through an adhesive layer 9, outside the othershorter latus 4A4 of the semiconductor chip 4.

The supporting lead 8A is subjected to a bending work for locating thechip fixation part of this supporting lead onto the side of the rearsurface of the semiconductor chip 4, while the supporting lead 8B issubjected to a bending work for locating the chip fixation part of thissupporting lead onto the side of the rear surface of the semiconductorchip 5.

The semiconductor device 2 thus constructed is manufactured by amanufacturing process which employs a lead frame LF2 shown in FIG. 14 (aplan view). The manufacture of the semiconductor device 2 of thisembodiment is somewhat different from the manufacturing processdescribed in the foregoing embodiment 1. More specifically, thesemiconductor chip 4 and the semiconductor chip 5 are bonded and fixedin the state in which the rear surfaces of these semiconductor chips arefaced to each other, and the respective semiconductor chips 4 and 5 arebonded and fixed to the supporting leads 8A and 8B, followed by wirebonding. The fixations between the supporting leads and thecorresponding semiconductor chips can be done in such a way that thesemiconductor chips 4 and 5 bonded and fixed are inserted aslant betweenthe supporting lead 8A and the supporting lead 8B.

The wire bonding step is performed in such a way that the electrodes 6of the semiconductor chip 4 and leads 10A are electrically connected bypieces of wire 11, and that the electrodes 6 of the semiconductor chip 5and leads 10B are thereafter electrically connected by pieces of wire11. Herein, the semiconductor chips 4 and 5 are bonded and fixed in thestate in which the positions of these semiconductor chips are staggeredin the direction of arraying the electrodes 6. Therefore, when theelectrodes 6 of the semiconductor chip 4 are connected with the leads10A by the wire pieces 11, a heat stage can be held in touch with, thepartial region of the rear surface of the semiconductor chip 4 opposingto the region of the side of one shorter latus 4A3 thereof, though notdirectly but through the supporting lead 8A. Besides, when theelectrodes 6 of the semiconductor chip 5 are connected with the leads10B by the wire pieces 11, the heat stage can be held in touch with thepartial region of the rear surface of the semiconductor chip 5 opposingto the region of the side of the other shorter latus 5A4 thereof, thoughnot directly but through the supporting lead 8B.

In this manner, the semiconductor chip 4 and the semiconductor chip 5are bonded and fixed to each other in the state in which the positionsof these semiconductor chips are staggered so that one shorter latus 4A3of the semiconductor chip 4 may lie outside one shorter latus 5A3 of thesemiconductor chip 5 and that the other shorter latus 5A4 of thesemiconductor chip 5 may lie outside the other shorter latus 4A4 of thesemiconductor chip 4, and the supporting lead 8A is bonded and fixed tothe rear surface of the semiconductor chip 4 outside one shorter latus5A3 of the semiconductor chip 5, while the supporting lead 8B is bondedand fixed to the rear surface of the semiconductor chip 5 outside theother shorter latus 4A4 of the semiconductor chip 4. Therefore, any tabdoes not exist between the semiconductor chip 4 and the semiconductorchip 5, so that a distance from the circuit forming surface 4A of thesemiconductor chip 4 to the circuit forming surface 5A of thesemiconductor chip 5 can be shortened.

Besides, since only one adhesive layer exists between the semiconductorchip 4 and the semiconductor chip 5, the distance from the circuitforming surface 4A of the semiconductor chip 4 to the circuit formingsurface 5A of the semiconductor chip 5 can be shortened.

In addition, the supporting lead 8A is bonded and fixed to the rearsurface of the semiconductor chip 4 led outside one shorter latus 5A3 ofthe semiconductor chip 5, and the supporting lead 8B is bonded and fixedto the rear surface of the semiconductor chip 5 led outside the othershorter latus 4A4 of the semiconductor chip 4, so that the thickness ofeach of the supporting leads 8A, 8B is cancelled by the thickness fromthe circuit forming surface 4A of the semiconductor chip 4 to thecircuit forming surface 5A of the semiconductor chip 5, and thethickness of the resin body 12 is not affected by the supporting leads8A, 8B.

As a result, effects similar to those of the foregoing embodiment 1 areattained.

Moreover, the semiconductor chip 4 and the semiconductor chip 5 arebonded and fixed in the state in which the positions of thesesemiconductor chips are staggered relatively to each other so that oneshorter latus 4A3 of the semiconductor chip 4 intersecting with onelonger latus 4A1 thereof may lie outside one shorter latus 5A3 of thesemiconductor chip 5 intersecting with one longer latus 5A1 thereof andlying on the same side as one shorter latus 4A3 of the semiconductorchip 4, and that the other shorter latus 5A4 of the semiconductor chip 5opposing to one shorter latus 5A3 thereof may lie outside the othershorter latus 4A4 of the semiconductor chip 4 opposing to one shorterlatus 4A3 thereof and lying on the same side as the other shorter latus5A4 of the semiconductor chip 5. At the wire bonding step, therefore,the area of touch between the rear surface of the semiconductor chip 4and the heat stage (24) increases, and hence, a time period for heatingthe semiconductor chip 4 at this step can be shortened. Also, the areaof touch between the rear surface of the semiconductor chip 5 and theheat stage (24) increases, and hence, a time period for heating thesemiconductor chip 5 can be shortened at the wire bonding step. As aresult, the production efficiency of the semiconductor device 2 can beheightened.

EMBODIMENT 3

FIG. 15 is a plan view of a semiconductor device being Embodiment 3 ofthe present invention in a state where the upper part of a resin bodyhas been removed, while FIG. 16 is a sectional view taken along line E—Eindicated in FIG. 15.

As illustrated in FIGS. 15 and 16, the semiconductor device 3 of thisembodiment has basically the same construction as that of Embodiment 2described before, but it differs from the foregoing embodiment inconstructional points explained below.

A supporting lead 8A is bonded and fixed on the side of one shorterlatus 4A3 of the circuit forming surface 4A of a semiconductor chip 4,while a supporting lead 8B is bonded and fixed on the side of the othershorter latus 5A4 of the circuit forming surface 5A of a semiconductorchip 5.

Although the supporting lead 8A is not subjected to any bending work,the supporting lead 8B is subjected to a bending work for locating thechip fixation part of this supporting lead onto the side of the circuitforming surface 5A of the semiconductor chip 5.

The semiconductor device 3 thus constructed is manufactured by amanufacturing process which employs a lead frame LF3 shown in FIG. 17 (aplan view). Likewise to the manufacturing process described in theforegoing embodiment 2, the manufacture of the semiconductor device 3 ofthis embodiment is so performed that the semiconductor chip 4 and thesemiconductor chip 5 are bonded and fixed in a state where the rearsurfaces of these semiconductor chips are faced to each other, and thatthe respective semiconductor chips 4 and 5 are bonded and fixed to thesupporting leads 8A and 8B, followed by wire bonding. The fixationsbetween the supporting leads and the corresponding semiconductor chipscan be done in such a way that the semiconductor chips 4 and 5 bondedand fixed are inserted aslant between the supporting lead 8A and thesupporting lead 8B.

The wire bonding step is performed in such a way that the electrodes 6of the semiconductor chip 4 and leads 10A are electrically connected bypieces of wire 11, and that the electrodes 6 of the semiconductor chip 5and leads 10B are thereafter electrically connected by pieces of wire11. Herein, the semiconductor chips 4 and 5 are bonded and fixed in astate where the positions of these semiconductor chips are relativelystaggered in the direction of arraying the electrodes 6, and thesupporting lead 8A is bonded and fixed on the side of one shorter latus4A3 of the circuit forming surface 4A of the semiconductor chip 4, whilethe supporting lead 8B is bonded and fixed on the side of the othershorter latus 5A4 of the circuit forming surface 5A of a semiconductorchip 5. Therefore, when the electrodes 6 of the semiconductor chip 4 areconnected with the leads 10A by the wire pieces 11, a heat stage can beheld in direct touch with the partial region of the rear surface of thesemiconductor chip 4 opposing to the region of the side of one shorterlatus 4A3 thereof. Besides, when the electrodes 6 of the semiconductorchip 5 are connected with the leads 10B by the wire pieces 11, the heatstage can be held in direct touch with the partial region of the rearsurface of the semiconductor chip 5 opposing to the region of the sideof the other shorter latus 5A4 thereof.

In this manner, the supporting lead 8A is bonded and fixed on the sideof one shorter latus 4A3 of the circuit forming surface 4A of thesemiconductor chip 4, while the supporting lead 8B is bonded and fixedon the side of the other shorter latus 5A4 of the circuit formingsurface 5A of the semiconductor chip 5. Therefore, any tab does notexist between the semiconductor chip 4 and the semiconductor chip 5, sothat a distance from the circuit forming surface 4A of the semiconductorchip 4 to the circuit forming surface 5A of the semiconductor chip 5 canbe shortened.

Besides, since only one adhesive layer exists between the semiconductorchip 4 and the semiconductor chip 5, the distance from the circuitforming surface 4A of the semiconductor chip 4 to the circuit formingsurface 5A of the semiconductor chip 5 can be shortened.

In addition, owing to the contrivance in which the supporting lead 8A isbonded and fixed on the side of one shorter latus 4A3 of the circuitforming surface 4A of the semiconductor chip 4, and in which thesupporting lead 8B is bonded and fixed on the side of the other shorterlatus 5A4 of the circuit forming surface 5A of the semiconductor chip 5,the thickness of the supporting lead 8A is cancelled by the loop heightof the wire pieces 11 for electrically connecting the electrodes 6 ofthe semiconductor chip 4 with the leads 10A, and the thickness of thesupporting lead 8B is cancelled by the loop height of the wire pieces 11for electrically connecting the electrodes 6 of the semiconductor chip 5with the leads 10B. Accordingly, the thickness of the resin body 12 isnot affected by the supporting leads 8A, 8B. As a result, effectssimilar to those of the foregoing embodiment 2 are attained.

By the way, even in the foregoing embodiment 1, the rear surfaces of thesemiconductor chips 4 and 5 may well be bonded and fixed in the state inwhich the positions of these semiconductor chips are relativelystaggered in the direction of arraying the electrodes 6, in the samemanner as in this embodiment 3. Also in this case, as in this embodiment3, the area of touch between the rear surface of the semiconductor chip4 and the heat stage increases, so that a time period for heating thesemiconductor chip 4 at the wiring bonding step, can be shortened.Besides, the area of touch between the rear surface of the semiconductorchip 5 and the heat stage increases, so that a time period for heatingthe semiconductor chip 5 can be shortened at the wire bonding step.

EMBODIMENT 4

FIG. 18 is a plan view of a semiconductor device being Embodiment 4 ofthe present invention in a state where the upper part of a resin bodyhas been removed, while FIG. 19 is a sectional view of the semiconductordevice.

As illustrated in FIGS. 18 and 19, the semiconductor device 30 of thisembodiment has basically the same construction as that of Embodiment 1described before, but it differs from the foregoing embodiment inconstructional points explained below.

Those parts 8X of supporting leads 8 which lie outside a semiconductorchip 4 are subjected to a bending work so that the thickness of theresin of the resin body 12 on the circuit forming surface 4A of thesemiconductor chip 4 may become less than the thickness of the resin ofthe resin body 12 on the circuit forming surface 5A of a semiconductorchip 5. Although the reason for executing such a bending work will bedetailed later, this bending work is intended to suppress thosefluctuations of the semiconductor chips in the vertical direction(stacked direction) thereof which are incurred by the flowage of theresin injected under pressure into the cavity of a metal mold, in caseof forming the resin body 12 on the basis of transfer molding.

The semiconductor device 30 of this embodiment is constructed having thetwo supporting leads 8, as in the foregoing embodiment 1. The twosupporting leads 8 extend from one shorter latus of the two shorterlatera of the resin body 12 opposing to each other, toward the othershorter latus, and they traverse the two shorter latera of the circuitforming surface 4A of the semiconductor chip 4 opposing to each other,respectively. The chip fixation part of one of the two supporting leads8 is bonded and fixed through an adhesive layer 9 on the side of onelonger latus 4A1 of the semiconductor chip 4, while the chip fixationpart of the other supporting lead 8 is bonded and fixed through anadhesive layer 9 on the side of the other longer latus 4A2 of thesemiconductor chip 4. That is, any adhesive layer for bonding and fixingthe supporting lead and the semiconductor chip is not provided on theinterspace between one supporting lead 8 and the other supporting lead8.

Meanwhile, an adhesive layer should be desirably performed the bondingfixation of the supporting lead and the semiconductor chip with thesmallest possible area, for the reason that moisture contained in thisadhesive layer is vaporized and expanded by heat which arises in atemperature cycle test being an environmental test after the completionof the product of the semiconductor device, or by solder reflow heatwhich arises when the semiconductor device is soldered and mounted on amounting substrate, thereby to form the factor of so-called “bodycracking” which brings about cracks in the resin body. In a case wherethe semiconductor chip is bonded and fixed to a tab, the area of arequired adhesive layer usually becomes larger in comparison with thatof the adhesive layer for the supporting lead though governed by thesize of the tab. It is therefore undesirable to support thesemiconductor chip by the tab. Accordingly, the semiconductor device ofhigh reliability and thinned structure can be offered by theconstruction in which the semiconductor chip 4 is bonded and fixed tothe supporting leads 8 as in this embodiment.

Next, the manufacture of the semiconductor device 30 will be describedwith reference to FIG. 20 thru FIG. 25. FIG. 20 is a plan view of a leadframe which is used in the manufacture of the semiconductor device, andFIGS. 21 thru 25 are sectional views for explaining a manufacturingprocess. Incidentally, actual lead frames have a multiple stringstructure so that a plurality of semiconductor devices can bemanufactured. For the brevity of illustration, however, FIG. 20 showsone domain where one semiconductor device is manufactured.

First, one semiconductor chip 4 is bonded and fixed onto the lead frameLF4. As shown in FIG. 21, the fixation between the lead frame LF4 andthe semiconductor chip 4 is done in such a way that the semiconductorchip 4 is set on a heat stage 31, that the circuit forming surface 4A ofthe semiconductor chip 4 is thereafter coated with an adhesive made of,for example, a thermosetting resin, thereby to form the adhesive layers9, and that the supporting leads 8 are thereafter secured onto thecircuit forming surface 4A of the semiconductor chip 4 bythermocompression with a bonding tool 32. On this occasion, the fixationis done in a state where the semiconductor chip 4 is oriented so thatone longer latus 4A1 of this semiconductor chip 4 may lie on the side ofleads 10A (on the side of one of two groups of leads opposing to eachother).

Incidentally, each of the adhesive layers 9 may well be formed using aninsulating resin film which is provided with adhesive layers on both itssurfaces (front surface and rear surface). In this case, however, theadhesive layer 9 thickens more than in the case of forming the adhesivelayer 9 by applying the adhesive. Therefore, such an expedient issomewhat demeritorious for thinning the semiconductor device.

Subsequently, the lead frame LF4 is turned upside down with the rearsurface of the semiconductor chip 4 facing upwards, whereupon thesemiconductor chip 5 is bonded and fixed to the semiconductor chip 4. Asshown in FIG. 22, the fixation between the semiconductor chip 4 and thesemiconductor chip 5 is done in such a way that the semiconductor chip 4is set on a heat stage 33 in a state where the heat stage 33 and thecircuit forming surface 4A of this semiconductor chip 4 face each other,that the rear surface of the semiconductor chip 4 is thereafter coatedwith an adhesive made of, for example, a silver (Ag) paste material,thereby to form an adhesive layer 7, and that the semiconductor chip 5is thereafter secured onto the rear surface of the semiconductor chip 4in a state where the rear surfaces of the semiconductor chips 4 and 5face each other. On this occasion, the fixation is done in a state wherethe semiconductor chip 5 is oriented so that one longer latus 5A1 ofthis semiconductor chip 5 may lie on the side of leads 10B (on the sideof the other of the two groups of leads opposing to each other).Besides, the fixation is done in a state where the positions of thesemiconductor chips 4 and 5 are staggered relatively to each other sothat one longer latus 4A1 of the, semiconductor chip 4 may lie outsidethe other longer latus 5A2 of the semiconductor chip 5, and that onelonger latus 5A1 of the semiconductor chip 5 may lie outside the otherlonger latus 4A2 of the semiconductor chip 4 (that is, in a state wherethe positions are relatively shifted in the direction in which onelonger latus 4A1 of the semiconductor chip 4 and one longer latus 5A1 ofthe semiconductor chip 5 come away from each other). The amount of thepositional shift between the semiconductor chips 4 and 5 shoulddesirably be to, the extent that the electrodes 6 of the semiconductorchip 4 lie outside the other longer latus 5A2 of the semiconductor chip5, and that the electrodes 6 of the semiconductor chip 5 lie outside theother longer latus 4A2 of the semiconductor chip 4.

Incidentally, the adhesive layer 7 may well be formed using aninsulating resin film which is provided with adhesive layers on both itssurfaces. In this case, however, the adhesive layer 7 thickens more thanin the case of forming the adhesive layer 7 by applying the adhesive.Therefore, such an expedient is somewhat demeritorious for thinning thesemiconductor device.

Subsequently, the lead frame LF4 is inverted upwards with the circuitforming surface 4A of the semiconductor chip 4 facing upwards, whereuponthe electrodes 6 of the semiconductor chip 4 and the leads 10A areelectrically connected by pieces of conductive wire 11. As shown in FIG.23, the connections between the electrodes 6 of the semiconductor chip 4and the leads 10A are done by setting the semiconductor chips 4 and 5 ona heat stage 34 in a state where the heat stage 34 and the circuitforming surface 5A of the semiconductor chip 5 face to each other. Gold(Au) wire, for example, is employed as the wire 11. Besides, a method ofconnecting the wire 11 is, for example, ball bonding (nailhead bonding)in which ultrasonic vibrations are used conjointly withthermocompression.

At this step, the partial region of the rear surface of thesemiconductor chip 4 opposing to the region thereof on the side of onelonger latus 4A1 of the circuit forming surface 4A is exposed.Therefore, the heat stage 34 is provided with a protrusion 34Bbeforehand so as to come into touch with the exposed partial region ofthe rear surface, whereby this partial region of the rear surface of thesemiconductor chip 4 can be held in direct touch with the heat stage 34.

More specifically, the rear surfaces of the respective semiconductorchips 4 and 5 are bonded and fixed to each other in the state ofstaggered positions in which one longer latus 4A1 of the semiconductorchip 4 lies outside the other longer latus 5A2 of the semiconductor chip5, and in which one longer latus 5A1 of the semiconductor chip 5 liesoutside the other longer latus 4A2 of the semiconductor chip 4, wherebythe partial region of the rear surface of the semiconductor chip 4 canbe held in direct touch with the heat stage 34, and the heat of the heatstage 34 is effectively conducted to the electrodes 6 of thesemiconductor chip 4, so that the inferior connections between theelectrodes 6 of the semiconductor chip 4 and the wire pieces 11 can berelieved.

Incidentally, at this step, the semiconductor chip 5 is set on the heatstage 34 in a state where its circuit forming surface 5A facesdownwards, so that the heat stage 34 is provided with a recess 34A inorder to prevent this heat stage 34 from coming into touch with theelectrodes 6 of the semiconductor chip 5.

Subsequently, the lead frame LF4 is turned upside down with the circuitforming surface 5A of the semiconductor chip 5 facing upwards, whereuponthe electrodes 6 of the semiconductor chip 5 and the leads 10B areelectrically connected by pieces of conductive wire 11. As shown in FIG.24, the connections between the electrodes 6 of the semiconductor chip 5and the leads 10B are done by setting the semiconductor chips 4 and 5 ona heat stage 35 in a state where the heat stage 35 and the circuitforming surface 4A of the semiconductor chip 4 face to each other. Gold(Au) wire, for example, is employed as the wire 11. Besides, a method ofconnecting the wire 11 is, for example, ball bonding in which ultrasonicvibrations are used conjointly with thermocompression.

At this step, the partial region of the rear surface of thesemiconductor chip 5 opposing to the region thereof on the side of onelonger latus 5A1 of the circuit forming surface 5A is exposed.Therefore, the heat stage 35 is provided with a protrusion 35Bbeforehand so as to come into touch with the exposed partial region ofthe rear surface, whereby this partial region of the rear surface of thesemiconductor chip 5 can be held in direct touch with the heat stage 35.

More specifically, the rear surfaces of the respective semiconductorchips 4 and 5 are bonded and fixed to each other in the state ofstaggered positions in which one longer latus 4A1 of the semiconductorchip 4 lies outside the other longer latus 5A2 of the semiconductor chip5, and in which one longer latus 5A1 of the semiconductor chip 5 liesoutside the other longer latus 4A2 of the semiconductor chip 4, wherebythe partial region of the rear surface of the semiconductor chip 5 canbe held in direct touch with the heat stage 35, and the heat of the heatstage 35 is effectively conducted to the electrodes 6 of thesemiconductor chip 5, so that the inferior connections between theelectrodes 6 of the semiconductor chip 5 and the wire pieces 11 can berelieved.

Besides, in the process thus far described, the first wire bonding stepof electrically connecting the electrodes 6 of the semiconductor chip 4with the leads 10A by the wire pieces 11, and the second wire bondingstep of electrically connecting the electrodes 6 of the semiconductorchip 5 with the leads 10B by the wire pieces 11 are carried out afterthe chip bonding step of forming the stacked chip assembly by bondingand fixing the semiconductor chip 5 to the semiconductor chip 4. InEmbodiment 1 described before, the first wire bonding step is performedbefore the chip bonding step of forming the stacked chip assembly, andhence, the drawback is liable to occur that the wire pieces 11 subjectedto the connection treatment at the first wire bonding step are deformedat the chip bonding step. On the other hand, in this embodiment 4, thefirst and second wire bonding steps are performed after the chip bondingstep, and hence, the wire deformations which appear at the chip bondingstep can be substantially excluded.

Incidentally, at this step, the semiconductor chip 4 is set on the heatstage 35 in a state where its circuit forming surface 4A facesdownwards, so that the heat stage 35 is provided with a recess 35A inorder to prevent this heat stage 35 from coming into touch with the wirepieces 11.

Subsequently, the lead frame LF4 is inverted upwards with the circuitforming surface 4A of the semiconductor chip 4 facing upwards.Thereafter, as shown in FIG. 25, the lead frame LF4 is positionedbetween the upper mold 36A and lower mold 36B of the metal mold 36 of atransfer molding equipment. On this occasion, the semiconductor chips 4,5, the inner portions of the leads 10A, the inner portions of the leads10B, the supporting leads 8, and the wire pieces 11 are arranged insidea cavity 37 which is defined by the upper mold 36A and the lower mold36B.

Subsequently, the resin body 12 is formed in such a way that a fluidresin (molten resin) is injected under pressure from the pot of themetal mold 36 into the cavity 37 through the runner, pouring gate etc.thereof. The semiconductor chips 4, 5, the inner portions of the leads10A, the inner portions of the leads 10B, the supporting leads 8, andthe wire pieces 11 are encapsulated with the resin body 12. Employed asthe resin is, for example, a biphenyl-based thermosetting resin which isdoped with a phenolic hardener, silicone rubber, a filler, or the like.

Meanwhile, the outer portions of leads function also to absorb and relaxstresses ascribable to thermal expansions arising when a semiconductordevice is mounted on a mounting substrate, and stresses ascribable tothe warp of the mounting substrate after the mounting. The stressrelaxing function degenerates as a distance from the emergent part ofeach lead emerging out of a resin body, to the mounting substrate,shortens with the thinning of the semiconductor device. In the thinningof the semiconductor device, therefore, the distance from the emergentpart of each lead to the mounting substrate should desirably belengthened to the utmost by locating the emergent part of each leadabove the central level of the resin body in the thickness directionthereof (the horizontal plane of the resin body at ½ of the thicknessthereof). Also in the semiconductor device 30 of this embodiment,accordingly, the emergent parts of the leads (10A, 10B) are locatedabove the central level of the resin, body 12 in the thickness directionthereof.

Such a structure is incarnated by locating the lead frame LF4 above thecentral level of the cavity 37 in the thickness direction thereof (thehorizontal plane of the cavity at ½ of the thickness thereof) asillustrated in FIG. 25. Here in the case where the lead frame LF4 islocated above the central level of the cavity 37 in the thicknessdirection thereof, upper and lower gates (also termed “center gates”)for injecting a resin from the upper side and lower side of a lead frameinto a cavity become difficult of adoption as the pouring gate 38, andhence, the lower gate for injecting the resin from the lower side of thelead frame LF4 is inevitably adopted.

On the other hand, for the purpose of suppressing failure to fill thecavity 37 with the resin, in other words, suppressing the appearance ofvoids, it is desirable to equalize a first distance from the circuitforming surface 4A of the semiconductor chip 4 to the inwall surface ofthe cavity 37 confronting this circuit forming surface 4A, with a seconddistance from the circuit forming surface 5A of the semiconductor chip 5to the inwall surface of the cavity 37 confronting this circuit formingsurface 5A. However, in the case where the resin body 12 having athickness of 1 [mm] or less is formed by adopting the lower gate, theside of the circuit forming surface 4A of the semiconductor chip 4 isfilled up with the resin earlier than the side of the circuit formingsurface 5A of the semiconductor chip 5. Therefore, the drawback isliable to occur that the semiconductor chips (4, 5) are pushed downwardsby the resin with which the side of the circuit forming surface 4A ofthe semiconductor chip 4 has been filled up, so the semiconductor chip5, the wire pieces 11, etc. are exposed out of the resin body 12. Thisdrawback forms a factor for incurring the lowering of the availablepercentage of the products of the semiconductor device.

The fluctuations of the semiconductor chips.(4, 5) in the verticaldirection can be suppressed by setting the first distance (the distancefrom the circuit forming surface 4A of the semiconductor chip 4 to theinwall surface of the cavity 37) shorter than the second distance (thedistance from the circuit forming surface 5A of the semiconductor chip 5to the inwall surface of the cavity 37). In this embodiment, therefore,the parts 8X of the supporting leads 8 are subjected to the bending workso that the first distance may become shorter than the second distance,in other words, that the resin thickness of the resin body 12 on thecircuit forming surface 4A of the semiconductor chip 4 may become lessthan the resin thickness on the circuit forming surface 5A of thesemiconductor chip 5.

Subsequently, the lead frame LF4 is taken out of the metal mold 36, atie bar 13 coupled to the leads 10A and a tie bar 13 coupled to theleads 10B are thereafter cut away, the outer portions of the respectiveleads 10A and 10B are thereafter cut away from the frame member 14 ofthe lead frame LF4, the outer portions of the respective leads 10A and10B are thereafter molded into, for example, a gull-wing shape being oneflat mounting shape, and the supporting leads 8 are thereafter cut awayfrom the frame member 14 of the lead frame LF4. In this way, thesemiconductor device 30 shown in FIGS. 18 and 19 is substantiallycompleted.

Incidentally, in a first chip bonding equipment for fixing thesemiconductor chips 4 to the lead frames LF4, the lead frames LF4 arereceived from a cassette holder 39A installed in a loader section, intoa cassette holder 39B installed in an unloader section, as illustratedin FIG. 26 (a schematic view). Also, in a second chip bonding equipmentfor fixing the semiconductor chips 5 to the semiconductor chips 4, thelead frames LF4 are received from the cassette holder 39B installed in aloader section, into a cassette holder 39C installed in an unloadersection, as illustrated in FIG. 27 (a schematic view). Besides, in afirst wire bonding equipment for electrically connecting the electrodes6 of the semiconductor chips 4 and the leads 10A by the wire pieces 11,the lead frames LF4 are received from the cassette holder 39C installedin a loader section, into a cassette holder 39D installed in an unloadersection, as illustrated in FIG. 28 (a schematic view). Also, in a secondwire bonding equipment for electrically connecting the electrodes 6 ofthe semiconductor chips 5 and the leads 10B by the wire pieces 11, thelead frames LF4 are received from the cassette holder 39D installed in aloader section, into a cassette holder 39E installed in an unloadersection, as illustrated in FIG. 29 (a schematic view).

After having received the lead frames LF4, the cassette holder 39Binstalled in the unloader section of the first chip bonding equipment isinstalled in the loader section of the second chip bonding equipment. Atthis time, the cassette holder 39B is inverted upwards and theninstalled, whereby the lead frames LF4 can be readily inverted at thesecond chip bonding step.

Also, after having received the lead frames LF4, the cassette holder 39Cinstalled in the unloader section of the second chip bonding equipmentis installed in the loader section of the first wire bonding equipment.At this time, the cassette holder 39C is inverted downwards and theninstalled, whereby the lead frames LF4 can be readily inverted at thefirst wire bonding step.

Besides, after having received the lead frames LF4, the cassette holder39D installed in the unloader section of the first wire bondingequipment is installed in the loader section of the second wire bondingequipment. At this time, the cassette holder 39D is inverted upwards andthen installed, whereby the lead frames LF4 can be readily inverted atthe second wire bonding step.

In this manner, the following effects are attained in accordance withthis embodiment:

(1) The chip fixation part of one supporting lead 8 is bonded and fixedon the side of one longer latus 4A1 of the semiconductor chip 4, whilethe chip fixation part of the other supporting lead 8 is bonded andfixed on the side of the other longer latus 4A2 of the semiconductorchip 4.

Owing to such a construction, the area of each adhesive layer 9 forbonding and fixing the semiconductor chip 4 to the correspondingsupporting lead 8 can be made small, and hence, the body cracking whichis ascribable to the vaporization and expansion of the moisture absorbedin the adhesive layer 9 can be suppressed. As a result, the reliabilityof the semiconductor device 30 can be enhanced.

(2) The part 8X of each supporting lead 8 is subjected to the bendingwork so that the resin thickness of the resin body 12 on the circuitforming surface 4A of the semiconductor chip 4 may become less than theresin thickness thereof on the circuit forming surface 5A of asemiconductor chip 5.

Owing to such a construction, even when the lower gate is adopted inorder to locate the lead frame LF4 above the central level of the cavity37 in the thickness direction thereof, in the case of forming the resinbody 12 of the thickness of 1 [mm] or less on the basis of the transfermolding, it is possible to suppress those fluctuations of thesemiconductor chips (4, 5) in the vertical direction thereof which areincurred by the flowage of the resin injected under pressure into thecavity 37, and accordingly to suppress the drawback that thesemiconductor chip 5, the wire pieces 11, etc. are exposed out of theresin body 12. As a result, the available percentage of the products ofthe semiconductor device 30 can be heightened.

(3) In the manufacture of the semiconductor device 30, the first wirebonding step of electrically connecting the electrodes 6 of thesemiconductor chip 4 with the leads 10A by the wire pieces 11, and thesecond wire bonding step of electrically connecting the electrodes 6 ofthe semiconductor chip 5 with the leads 10B by the wire pieces 11 arecarried out after the chip bonding step of bonding and fixing thesemiconductor chip 5 to the semiconductor chip 4.

Thus, the wire deformations which appear at the chip bonding step can besubstantially excluded, so that the available percentage of the productsof the semiconductor device 30 can be heightened.

EMBODIMENT 5

FIG. 30 is a plan view of a semiconductor device being Embodiment 5 ofthe present invention in a state where the upper part of a resin bodyhas been removed, while FIG. 31 is a sectional view of the semiconductordevice.

As illustrated in FIGS. 30 and 31, the semiconductor device 40 of thisembodiment has basically the same construction as that of Embodiment 1described before, but it differs from the foregoing embodiment inconstructional points explained below.

Semiconductor chips 4 and 5 are stacked in a state where the rearsurfaces of these semiconductor chips are faced to each other so thatone longer latus 4A1 of the semiconductor chip 4 and the other longerlatus 5A2 of the semiconductor chip 5 may confront the side of leads10A, and besides, where the positions of these semiconductor chips arestaggered relatively to each other so that the other longer latus 4A2 ofthe semiconductor chip 4 may lie outside one longer latus 5A1 of thesemiconductor chip 5 and that the other longer latus 5A2 of thesemiconductor chip 5 may lie outside one longer latus 4A1 of thesemiconductor chip 4 (that is, where the positions are relativelyshifted in the direction in which one longer latus 4A1 of thesemiconductor chip 4 and one longer latus 5A1 of the semiconductor chip5 come near to each other).

In addition, the semiconductor chips 4 and 5 have not their rearsurfaces bonded and fixed to each other, but they are stacked with theirrear surfaces held in touch with each other.

Yet in addition, each of the plurality of leads 10A is such that thedistal end part of its inner portion lying within the resin body 12 isbonded and fixed to the rear surface of the semiconductor chip 5 throughan adhesive layer 9 outside one longer latus 4A1 of the semiconductorchip 4, and each of a plurality of leads 10B is such that the distal endpart of its inner portion lying within the resin body 12 is bonded andfixed to the rear surface of the semiconductor chip 4 through anadhesive layer 9 outside one longer latus 5A1 of the semiconductor chip5.

Further, those wire connection surfaces of the leads 10A to which piecesof wire 11 are connected lie nearer to the side of the semiconductorchip 5 with respect to the circuit forming surface 4A of thesemiconductor chip 4, while those wire connection surfaces of the leads10B to which pieces of wire 11 are connected lie nearer to the side ofthe semiconductor chip 4 with respect to the circuit forming surface 5Aof the semiconductor chip 5.

Still further, the inner portion of each lead 10A is constructed havinga first part 10A1 which traverses the longer latus of the rear surfaceof the semiconductor chip 5 lying outside one longer latus 4A1 of thesemiconductor chip 4 and which is bonded and fixed to this rear surface,a second part 10A2 which bends from the first part 10A1 to the side ofthe circuit forming surface 4A of the semiconductor chip 4, and a thirdpart 10A3 which extends from the second part 10A2 in the same directionas the extending direction of the first part 10A1. Likewise, the innerportion of each lead 10B is constructed having a first part 10B1 whichtraverses the longer latus of the rear surface of the semiconductor chip4 lying outside one longer latus 5A1 of the semiconductor chip 5 andwhich is bonded and fixed to this rear surface, a second part 10B2 whichbends from the first part 10B1 to the side of the circuit formingsurface 4A of the semiconductor chip 4, and a third part 10B3 whichextends from the second part 10B2 in the same direction as the extendingdirection of the first part 10B1. The third part 10A3 of each lead 10Aand the third part 10B3 of each lead 10B lie above the central level ofthe resin body 12 in the thickness direction thereof (the horizontalplane of the resin body 12 at ½ of the thickness thereof) (that is, thethird parts 10A3 and 10B3 lean toward the side of the upper surface 12Aof the resin body 12).

Yet further, a supporting lead 8C is arranged outside one shorter latusof the two shorter latera of the semiconductor chip 4 opposing to eachother, while a supporting lead 8D is arranged outside the other shorterlatus. Unlike the supporting leads explained in the foregoingembodiments, the supporting leads 8C and 8D serve to support the resinbody 12 on a lead frame in a manufacturing process for the semiconductordevice 40.

The manufacture of the semiconductor device 40 of this embodimentproceeds so that the region of the rear surface of the semiconductorchip 4 opposing to the region of the side of the other longer latus 4A2of the circuit forming surface 4A of this semiconductor chip 4 is bondedand fixed to the first parts 10B1 of the leads 10B through the adhesivelayer 9, while the partial region of the rear surface of thesemiconductor chip 5 opposing to the region of the side of the otherlonger latus 5A2 of the circuit forming surface 5A of this semiconductorchip 5 is bonded and fixed to the first parts 10A1 of the leads 10Athrough the adhesive layer 9, and that the electrodes 6 of thesemiconductor chip 4 and the first parts 10A1 of the leads 10A areelectrically connected by the wire pieces 11, while the electrodes 6 ofthe semiconductor chip 5 and the first parts 10B1 of the leads 10B areelectrically connected by the wire pieces 11. In the manufacture of thesemiconductor device 40, the semiconductor chip 4 is supported on theframe member of the lead frame through the leads 10A, and thesemiconductor chip 5 is supported on the frame member of the lead framethrough the leads 10B.

In this manner, the following effects are attained in accordance withthis embodiment:

(1) The semiconductor chips 4 and 5 are stacked in the state in whichthe rear surfaces of these semiconductor chips are faced to each otherso that one longer latus 4A1 of the semiconductor chip 4 and the otherlonger latus 5A2 of the semiconductor chip 5 may confront the side ofthe leads 10A, and in which the positions of these semiconductor chipsare staggered relatively to each other so that the other longer latus4A2 of the semiconductor chip 4 may lie outside one longer latus 5A1 ofthe semiconductor chip 5 and that the other longer latus 5A2 of thesemiconductor chip 5 may lie outside one longer latus 4A1 of thesemiconductor chip 4, and moreover, each of the plurality of leads 10Ais such that the distal end part (the first part 10A1) of its innerportion lying within the resin body 12 is bonded and fixed to the rearsurface of the semiconductor chip 5 outside one longer latus 4A1 of thesemiconductor chip 4, while each of the plurality of leads 10B is suchthat the distal end part (the first part 10B1) of its inner portionlying within the resin body 12 is bonded and fixed to the rear surfaceof the semiconductor chip 4 outside one longer latus 5A1 of thesemiconductor chip 5.

Owing to such a construction, the length of each of the leads (10A, 10B)in the inner portion (the length of each lead extending from the outerperiphery of the resin body 12 toward the outer periphery of thesemiconductor chip) increases. It is therefore possible to suppresscorrosion arising at the wire connection parts of the leads (10A, 10B)and the electrodes 6 of the semiconductor chips (4, 5) due to moisturewhich invades the semiconductor device from outside with paths being theinterfaces between the resin of the resin body 12 and the leads. As aresult, the reliability of the semiconductor device 40 can be enhanced.

Besides, the semiconductor chip 4 is supported by the distal end parts(10B1) of the plurality of leads 10B, while the semiconductor chip 5 issupported by the distal end parts (10A1) of the plurality of leads 10A,so that the bonding fixation of the respective semiconductor chips 4, 5can be dispensed with, in other words, that an adhesive layer can beomitted. As a result, thinning in the structure of the semiconductordevice 40 and curtailment in the cost thereof can be achieved.

(2) Those wire connection surfaces of the leads 10A to which the wirepieces 11 are connected lie nearer to the side of the semiconductor chip5 with respect to the circuit forming surface 4A of the semiconductorchip 4, while those wire connection surfaces of the leads 10B to whichthe wire pieces 11 are connected lie nearer to the side of thesemiconductor chip 4 with respect to the circuit forming surface 5A ofthe semiconductor chip 5.

Owing to such a construction, the loop height of the wire pieces 11 (aheight from the circuit forming surface 4A of the semiconductor chip 4to the uppermost parts of the wire pieces) for electrically connectingthe electrodes 6 of the semiconductor chip 4 with the leads 10Adecreases, so that the resin thickness of the resin body 12 can bereduced on the side of the circuit forming surface 4A of thesemiconductor chip 4. Likewise, the loop height of the wire pieces 11 (aheight from the circuit forming surface 5A of the semiconductor chip 5to the lowermost parts of the wire pieces) for electrically connectingthe electrodes 6 of the semiconductor chip 5 with the leads 10Bdecreases, so that the resin thickness of the resin body 12 can bereduced on the side of the circuit forming surface 5A of thesemiconductor chip 5. As a result, thinning in the structure of thesemiconductor device 40 can be achieved.

(3) The inner portion of each lead 10A is constructed having the firstpart 10A1 which traverses the longer latus of the rear surface of thesemiconductor chip 5 lying outside one longer latus 4A1 of thesemiconductor chip 4 and which is bonded and fixed to this rear surface,the second part 10A2 which bends from the first part 10A1 to the side ofthe circuit forming surface 4A of the semiconductor chip 4, and thethird part 10A3 which extends from the second part 10A2 in the samedirection as the extending direction of the first part 10A1. Also, theinner portion of each lead 10B is constructed having the first part 10B1which traverses the longer latus of the rear surface of thesemiconductor chip 4 lying outside one longer latus 5A1 of thesemiconductor chip 5 and which is bonded and fixed to this rear surface,the second part 10B2 which bends from the first part 10B1 to the side ofthe circuit forming surface 4A of the semiconductor chip 4, and thethird part 10B3 which extends from the second part 10B2 in the samedirection as the extending direction of the first part 10B1.

Owing to such a construction, the emergent parts of the leads (10A, 10B)emerging out of the resin body 12 can be located above the central levelof this resin body 12 in the thickness direction thereof, so that thereliability of the semiconductor device 40 in mounting operations andthe reliability thereof after the mounting can be enhanced.

Incidentally, although the example in which the bonding fixation of thesemiconductor chips 4, 5 is omitted has been described in thisembodiment, the rear surfaces of the semiconductor chips 4, 5 may wellbe bonded and fixed through an adhesive layer 7 as illustrated in FIG.32 (a sectional view). In this case, the drawback can be suppressedthat, in forming the resin body 12 on the basis of transfer molding, thesemiconductor chips 4 and 5 separates due to the flowage of the resininjected under pressure into the cavity of a metal mold. Therefore, theavailable percentage of the products of the semiconductor device 40 canbe heightened, but the thickness of the semiconductor device 40increases instead.

EMBODIMENT 6

FIG. 33 is a sectional view of a semiconductor device being Embodiment 6of the present invention.

As illustrated in FIG. 33, the semiconductor device 41 of thisembodiment has basically the same construction as that of Embodiment 5described before, but it differs from the foregoing embodiment inconstructional points explained below.

Semiconductor chips 4 and 5 are stacked in a state where the rearsurfaces of these semiconductor chips are faced to each other so thatone longer latus 4A1 of the semiconductor chip 4 and the other longerlatus 5A2 of the semiconductor chip 5 may, confront the side of leads10A, and besides, where the positions of these semiconductor chips arestaggered relatively to each other so that one longer latus 4A1 of thesemiconductor chip 4 may lie outside the other longer latus 5A2 of thesemiconductor chip 5 and that one longer latus 5A1 of the semiconductorchip 5 may lie outside the other longer latus 4A2 of the semiconductorchip 4 (that is, where the positions are relatively shifted in thedirection in which one longer latus 4A1 of the semiconductor chip 4 andone longer latus 5A1 of the semiconductor chip 5 come away from eachother).

In addition, each of the plurality of leads 10A is such that the distalend part of its inner portion lying within a resin body 12 is bonded andfixed to the rear surface of the semiconductor chip 4 through anadhesive layer 9 outside the other longer latus 5A2 of the semiconductorchip 5, and each of a plurality of leads 10B is such that the distal endpart of its inner portion lying within the resin body 12 is bonded andfixed to the rear surface of the semiconductor chip 5 through anadhesive layer 9 outside the other longer latus 4A2 of the semiconductorchip 4.

The inner portion of each lead 10A is constructed having a first part10A1 which traverses the longer latus of the rear surface of thesemiconductor chip 4 lying outside the other longer latus 5A2 of thesemiconductor chip 5 and which is bonded and fixed to this rear surface,a second part 10A2 which bends from the first part 10A1 to the side ofthe circuit forming surface 4A of the semiconductor chip 4, and a thirdpart 10A3 which extends from the second part 10A2 in the same directionas the extending direction of the first part 10A1. Likewise, the innerportion of each lead 10B is constructed having a first part 10B1 whichtraverses the longer latus of the rear surface of the semiconductor chip5 lying outside the other longer latus 4A2 of the semiconductor chip 4and which is bonded and fixed to this rear surface, a second part 10B2which bends from the first part 10B1 to the side of the circuit formingsurface 4A of the semiconductor chip 4, and a third part 10B3 whichextends from the second part 10B2 in the same direction as the extendingdirection of the first part 10B1. The third part 10A3 of each lead 10Aand the third part 10B3 of each lead 10B lie above the central level ofthe resin body 12 in the thickness direction thereof (that is, the thirdparts 10A3 and 10B3 lie on the side of the upper surface 12A of theresin body 12).

The manufacture of the semiconductor device 41 of this embodiment issomewhat different from the manufacturing process described in theforegoing embodiment 5. The first parts 10A1 of the leads 10A are bondedand fixed to the region of the rear surface of the semiconductor chip 4opposing to the region of the side of one longer latus 4A1 of thecircuit forming surface 4A of this semiconductor chip 4, while the firstparts 10B1 of the leads 10B are bonded and fixed to the region of therear surface of the semiconductor chip 5 opposing to the region of theside of one longer latus 5A1 of the circuit forming surface 5A of thissemiconductor chip 5, followed by wire bonding.

According to the semiconductor device 41 of this embodiment thusconstructed, effects similar to those of the foregoing embodiment 5 areattained.

Moreover, each of the plurality of leads 10A is such that the distal endpart of its inner portion lying within the resin body 12 is bonded andfixed to the rear surface of the semiconductor chip 4 through theadhesive layer 9 outside the other longer latus 5A2 of the semiconductorchip 5, so that in electrically connecting the electrodes 6 of thesemiconductor chip 4 with the inner portions of the leads 10A by thewire pieces 11, a bonding stage can be held in touch with the distal endparts of the inner portions of the leads 10A, so as to effectivelyconduct the heat of the bonding stage to the electrodes 6 of thesemiconductor chip 4.

Besides, each of the plurality of leads 10B is such that the distal endpart of its inner portion lying within the resin body 12 is bonded andfixed to the rear surface of the semiconductor chip 5 through theadhesive layer 9 outside the other longer latus 4A2 of the semiconductorchip 4, so that in electrically connecting the electrodes 6 of thesemiconductor chip 5 with the inner portions of the leads 10B by thewire pieces 11, a bonding stage can be held in touch with the distal endparts of the inner portions of the leads 10B, so as to effectivelyconduct the heat of the bonding stage to the electrodes 6 of thesemiconductor chip 5.

As a result, the inferior connections between the electrodes 6 of thesemiconductor chip 4 and the wire pieces 11 can be relieved, and theinferior connections between the electrodes 6 of the semiconductor chip5 and the wire pieces 11 can be relieved, so that the availablepercentage of the products of the semiconductor device 41 can beheightened.

By the way, even in the semiconductor device 41 of this embodiment, therear surfaces of the semiconductor chips 4, 5 may well be bonded andfixed through an adhesive layer 7 as illustrated in FIG. 34 (a sectionalview).

EMBODIMENT 7

FIG. 35 is a plan view of a semiconductor device being Embodiment 7 ofthe present invention in a state where the upper part of a resin bodyhas been removed, while FIG. 36 is a sectional view of the semiconductordevice.

As illustrated in FIGS. 35 and 36, the semiconductor device 42 of thisembodiment has basically the same construction as that of Embodiment 5described before, but it differs from the foregoing embodiment inconstructional points explained below.

Each of a plurality of leads 10B is such that the distal end part of itsinner portion lying within the resin body 12 is bonded and fixed throughan adhesive layer 9 to the circuit forming surface 4A of thesemiconductor chip 4 and on the side of the other longer latus 4A2thereof.

Besides, the inner portion of each lead 10B is constructed having afirst part 10B1 which traverses the other longer latus 4A2 of thesemiconductor chip 4 lying outside one longer latus 5A1 of thesemiconductor chip 5 and which is bonded and fixed to this circuitforming surface 4A, a second part 10B2 which bends from the first part10B1 to the side of the rear surface of the semiconductor chip 4, and athird part 10B3 which extends from the second part 10B2 in the samedirection as the extending direction of the first part 10B1. The thirdpart 10A3 of each lead 10A and the third part 10B3 of each lead 10B lieabove the central level of the resin body 12 in the thickness directionthereof (the horizontal plane of the resin body 12 at ½ of the thicknessthereof) (that is, the third parts 10A3 and 10B3 lie on the side of theupper surface 12A of the resin body 12).

The manufacture of the semiconductor device 42 of this embodiment issomewhat different from the manufacturing process described in theforegoing embodiment 5. The first parts 10B1 of the leads 10B are bondedonto the side of the other longer latus 4A2 of the circuit formingsurface 4A of this semiconductor chip 4, and the first parts 10A1 of theleads 10A are bonded to the region of the rear surface of thesemiconductor chip 5 opposing to the region thereof on the side of theother longer latus 5A2 of the circuit forming surface 5A of thissemiconductor chip 5, followed by wire bonding.

According to the semiconductor device 42 of this embodiment thusconstructed, effects similar to those of the foregoing embodiment 5 areattained.

By the way, even in the semiconductor device 42 of this embodiment, therear surfaces of the semiconductor chips 4, 5 may well be bonded andfixed through an adhesive layer 7 as illustrated in FIG. 37 (a sectionalview).

EMBODIMENT 8

FIG. 38 is a plan view of a semiconductor device being Embodiment 8 ofthe present invention in a state where the upper part of a resin bodyhas been removed, while FIG. 39 is a sectional view of the semiconductordevice.

As illustrated in FIGS. 38 and 39, the semiconductor device 43 of thisembodiment has basically the same construction as that of Embodiment 5described before, but it differs from the foregoing embodiment inconstructional points explained below.

Semiconductor chips 4 and 5 are stacked in a state where the rearsurface of these semiconductor chip 4 and the circuit forming surface 5Aof the semiconductor chip 5 are faced to each other so that one longerlatus 4A1 of the semiconductor chip 4 and the other longer latus 5A2 ofthe semiconductor chip 5 may confront the side of leads 10A, andbesides, where the positions of these semiconductor chips are staggeredrelatively to each other so that one longer latus 4A1 of thesemiconductor chip 4 may lie outside the other longer latus 5A2 of thesemiconductor chip 5 and that one longer latus 5A1 of the semiconductorchip 5 may lie outside the other longer latus 4A2 of the semiconductorchip 4 (that is, where the positions are relatively shifted in thedirection in which one longer latus 4A1 of the semiconductor chip 4 andone longer latus 5A1 of the semiconductor chip 5 come away from eachother).

In addition, each of the plurality of leads 10A is such that the distalend part of its inner portion, lying within the resin body 12 is bondedand fixed to the rear surface of the semiconductor chip 4 through anadhesive layer 9 outside the other longer latus 5A2 of the semiconductorchip 5. Each of a plurality of leads 10B is such that the distal endpart of its inner portion lying within the resin body 12 is bonded andfixed to the rear surface of the semiconductor chip 5 through anadhesive layer 9 outside the other longer latus 4A2 of the semiconductorchip 4.

Besides, the inner portion of each lead 10A is constructed having afirst part 10A1 which traverses the longer latus of the rear surface ofthe semiconductor chip 4 lying outside the other longer latus 5A2 of thesemiconductor chip 5 and which is bonded and fixed to this rear surface,a second part 10A2 which bends from the first part 10A1 to the side ofthe circuit forming surface 4A of the semiconductor chip 4, and a thirdpart 10A3 which extends from the second part 10A2 in the same directionas the extending direction of the first part 10A1. Also, the innerportion of each lead 10B is constructed having a first part 10B1 whichtraverses the longer latus of the rear surface of the semiconductor chip5 lying outside the other longer latus 4A2 of the semiconductor chip 4and which is bonded and fixed to this rear surface, a second part 10B2which bends from the first part 10B1 to the side of the circuit formingsurface 4A of the semiconductor chip 4, and a third part 10B3 whichextends from the second part 10B2 in the same direction as the extendingdirection of the first part 10B1. The third part 10A3 of each lead 10Aand the third part 10B3 of each lead 10B lie above the central level ofthe resin body 12 in the thickness direction thereof (that is, the thirdparts 10A3 and 10B3 lie on the side of the upper surface 12A of theresin body 12).

The manufacture of the semiconductor device 43 of this embodiment issomewhat different from the manufacturing process described in theforegoing embodiment 5. The first parts 10B1 of the leads 10B are bondedonto the region of the rear surface of the semiconductor chip 5 opposingto the region thereof on the side of one longer latus 5A1 of the circuitforming surface 5A of this semiconductor chip 5, and the first parts10A1 of the leads 10A are thereafter bonded onto the region of the rearsurface of the semiconductor chip 4 opposing to the region thereof onthe side of one longer latus 4A1 of the circuit forming surface 4 ofthis semiconductor chip 4, followed by wire bonding.

According to the semiconductor device 43 of this embodiment thusconstructed, effects similar to those of the foregoing embodiment 5 areattained.

Moreover, each of the plurality of leads 10A is such that the distal endpart of its inner portion lying within the resin body 12 is bonded andfixed to the rear surface of the semiconductor chip 4 through theadhesive layer 9 outside the other longer latus 5A2 of the semiconductorchip 5, so that in electrically connecting the electrodes 6 of thesemiconductor chip 4 with the inner portions of the leads 10A by piecesof wire 11, a bonding stage can be held in touch with the distal endparts of the inner portions of the leads 10A, so as to effectivelyconduct the heat of the bonding stage to the electrodes 6 of thesemiconductor chip 4.

Besides, each of a plurality of leads 10B is such that the distal endpart of its inner portion lying within the resin body 12 is bonded andfixed to the rear surface of the semiconductor chip 5 through theadhesive layer 9 outside the other longer latus 4A2 of the semiconductorchip 4, so that in electrically connecting the electrodes 6 of thesemiconductor chip 5 with the inner portions of the leads 10B by piecesof wire 11, a bonding stage can be held in touch with the distal endparts of the inner portions of the leads 10B, so as to effectivelyconduct the heat of the bonding stage to the electrodes 6 of thesemiconductor chip 5.

As a result, the inferior connections between the electrodes 6 of thesemiconductor chip 4 and the wire pieces 11 can be relieved, and theinferior connections between the electrodes 6 of the semiconductor chip5 and the wire pieces 11 can be relieved, so that the availablepercentage of the products of the semiconductor device 43 can beheightened.

By the way, even in the semiconductor device 43 of this embodiment, therear surface of the semiconductor chip 4 and the circuit forming surface5A of the semiconductor chip 5 may well be bonded and fixed through anadhesive layer 7 as illustrated in FIG. 40 (a sectional view).

EMBODIMENT 9

FIG. 41 is a plan view of a semiconductor device being Embodiment 9 ofthe present invention in a state where the upper part of a resin bodyhas been removed, while FIG. 42 is a sectional view of the semiconductordevice.

As illustrated in FIGS. 41 and 42, the semiconductor device 44 of thisembodiment has basically the same construction as that of Embodiment 4described before, but it differs from the foregoing embodiment inconstructional points explained below.

Semiconductor chips 4 and 5 are stacked in a state where the rearsurfaces of these semiconductor chips are faced to each other so thatone longer latus 4A1 of the semiconductor chip 4 and the other longerlatus 5A2 of the semiconductor chip 5 may confront the side of leads10A, and besides, where the positions of these semiconductor chips arestaggered relatively to each other so that the other longer latus 4A2 ofthe semiconductor chip 4 may lie outside one longer latus 5A1 of thesemiconductor chip 5 and that the other longer latus 5A2 of thesemiconductor chip 5 may lie outside one longer latus 4A1 of thesemiconductor chip 4 (that is, where the positions are relativelyshifted in the direction in which one longer latus 4A1 of thesemiconductor chip 4 and one longer latus 5A1 of the semiconductor chip5 come near to each other).

In addition, the semiconductor chips 4 and 5 have not their rearsurfaces bonded and fixed to each other, but they are stacked with theirrear surfaces held in touch with each other.

The semiconductor device 44 of this embodiment is constructed having thetwo supporting leads 8, as in the foregoing embodiment 4. The chipfixation part of one 8E of the two supporting leads 8 is bonded andfixed through an adhesive layer 9 onto the region of the rear surface ofthe semiconductor chip 4 opposing to the region thereof on the side ofthe other longer latus 4A2 of the circuit forming surface 4A of thissemiconductor chip 4, outside one longer latus 5A1 of the semiconductorchip 5. Also, the chip fixation part of the other supporting lead 8F isbonded and fixed through an adhesive layer 9 onto the region of the rearsurface of the semiconductor chip 5 opposing to the region thereof onthe side of the other longer latus 5A2 of the circuit forming surface 5Aof this semiconductor chip 5, outside one longer latus 4A1 of thesemiconductor chip 4.

The parts 8X of one supporting lead 8E are subjected to a bending workfor locating the chip fixation part of this supporting lead onto theside of the rear surface of the semiconductor chip 4. Also, the parts 8Xof the other supporting lead 8F are subjected to a bending work forlocating the chip fixation part of this supporting lead onto the side ofthe rear surface of the semiconductor chip 5.

The manufacture of the semiconductor device 44 of this embodimentproceeds so that the region of the rear surface of the semiconductorchip 4 opposing to the region of the side of the other longer latus 4A2of the circuit forming surface 4A of this semiconductor chip 4 is bondedand fixed to the chip fixation part of one supporting lead 8E throughthe adhesive layer 9, while the region of the rear surface of thesemiconductor chip 5 opposing to the region of the side of the otherlonger latus 5A2 of the circuit forming surface 5A of this semiconductorchip 5 is bonded and fixed to the chip fixation part of the othersupporting lead 8F through the adhesive layer 9, and that the electrodes6 of the semiconductor chip 4 and the distal end parts of the innerportions of the leads 10A are electrically connected by pieces of wire11, while the electrodes 6 of the semiconductor chip 5 and the distalend parts of the inner portions of leads 10B are electrically connectedby pieces of wire 11. In the manufacture of the semiconductor device 44,the semiconductor chip 4 is supported on the frame member of a leadframe through one supporting lead 8E, and the semiconductor chip 5 issupported on the frame member of the lead frame through the othersupporting lead 8F.

According to the semiconductor device 44 of this embodiment thusconstructed, effects similar to those of the foregoing embodiment 5 areattained.

Moreover, the semiconductor chip 4 is supported by one supporting lead8E, while the semiconductor chip 5 is supported by the other supportinglead 8F, so that the bonding fixation of the respective semiconductorchips 4, 5 can be dispensed with, in other words, that an adhesive layercan be omitted. As a result, thinning in the structure of thesemiconductor device 44 and curtailment in the cost thereof can beachieved.

By the way, even in the semiconductor device 44 of this embodiment, therear surfaces of the semiconductor chips 4 and 5 may well be bonded andfixed through an adhesive layer.

EMBODIMENT 10

FIG. 43 is a sectional view of a semiconductor device being Embodiment10 of the present invention.

As illustrated in FIG. 43, the semiconductor device 45 of thisembodiment has basically the same construction as that of Embodiment 9described above, but it differs from the foregoing embodiment inconstructional points explained below.

Semiconductor chips 4 and 5 are stacked in a state where the rearsurfaces of these semiconductor chips are faced to each other so thatone longer latus. 4A1 of the semiconductor chip 4 and the other longerlatus 5A2 of the semiconductor chip 5 may confront the side of leads10A, and besides, where the positions of these semiconductor chips arestaggered relatively to each other so that one longer latus 4A1 of thesemiconductor chip 4 may lie outside the other longer latus 5A2 of thesemiconductor chip 5 and that one longer latus 5A1 of the semiconductorchip 5 may lie outside the other longer latus 4A2 of the semiconductorchip 4 (that is, where the positions are relatively shifted in thedirection in which one longer latus 4A1 of the semiconductor chip 4 andone longer latus 5A1 of the semiconductor chip 5 come away from eachother).

The semiconductor device 45 of this embodiment is constructed having thetwo supporting leads 8, as in the foregoing embodiment 9. The chipfixation part of one 8E of the two supporting leads 8 is bonded andfixed through an adhesive layer 9 onto the circuit forming surface 4A ofthe semiconductor chip 4 on the side of one longer latus 4A1 of thissemiconductor chip. Also, the chip fixation part of the other supportinglead 8F is bonded and fixed through an adhesive layer 9 onto the circuitforming surface 5A of the semiconductor chip 5 on the side of one longerlatus 4A1 of this semiconductor chip.

Parts of one supporting lead 8E are subjected to a bending work forlocating the chip fixation part of this supporting lead onto the side ofthe circuit forming surface 4A of the semiconductor chip 4. Also, partsof the other supporting lead 8F are subjected to a bending work forlocating the chip fixation part of this supporting lead onto the side ofthe circuit forming surface 5A of the semiconductor chip 5.

The manufacture of the semiconductor device 45 of this embodimentproceeds so that the semiconductor chips 4 and 5 are respectivelyinserted aslant between the supporting lead 8E and the supporting lead8F, that the supporting lead 8E is bonded and fixed to the circuitforming surface 4A of the semiconductor chip 4A, while the supportinglead 8F is bonded and fixed to the circuit forming surface 5A of thesemiconductor chip 5A, and that the electrodes 6 of the semiconductorchip 4 and the distal end parts of the inner portions of the leads 10Aare electrically connected by pieces of wire 11, while the electrodes 6of the semiconductor chip 5 and the distal end parts of the innerportions of leads 10B are electrically connected by pieces of wire 11.In the manufacture of the semiconductor device 45, the semiconductorchip 4 is supported on the frame member of a lead frame through onesupporting lead 8E, and the semiconductor chip 5 is supported on theframe member of the lead frame through the other supporting lead 8F.

According to the semiconductor device 45 of this embodiment thusconstructed, effects similar to those of the foregoing embodiment 9 areattained.

Moreover, the semiconductor chips 4 and 5 are stacked in the state wherethe positions of these semiconductor chips are relatively shifted in thedirection in which one longer latus 4A1 of the semiconductor chip 4 andone longer latus 5A1 of the semiconductor chip 5 come away from eachother, so that in electrically connecting the electrodes 6 of thesemiconductor chip 4 with the inner portions of the leads 10A by thewire pieces 11, a heat stage can be held in touch with the partialregion of the rear surface of the semiconductor chip 4 opposing to theelectrodes 6 thereof, so as to effectively conduct the heat of the heatstage to the electrodes 6 of the semiconductor chip 4.

Besides, in electrically connecting the electrodes 6 of thesemiconductor chip 5 with the inner portions of the leads 10B by thewire pieces 11, a heat stage can be held in touch with the partialregion of the rear surface of the semiconductor chip 5 opposing to theelectrodes 6 thereof, so as to effectively conduct the heat of the heatstage to the electrodes 6 of the semiconductor chip 5.

As a result, the inferior connections between the electrodes 6 of thesemiconductor chip 4 and the wire pieces 11 can be relieved, and theinferior connections between the electrodes 6 of the semiconductor chip5 and the wire pieces 11 can be relieved, so that the availablepercentage of the products of the semiconductor device 45 can beheightened.

By the way, even in the semiconductor device 45 of this embodiment, therear surfaces of the semiconductor chips 4 and 5 may well be bonded andfixed through an adhesive layer.

EMBODIMENT 11

FIG. 44 is a sectional view of a semiconductor device being Embodiment11 of the present invention.

As illustrated in FIG. 44, the semiconductor device 50 of thisembodiment has basically the same construction as that of Embodiment 10described above, but it differs from the foregoing embodiment inconstructional points explained below.

The semiconductor device 50 is constructed having a tab 54. Asemiconductor chip 4 has its rear surface bonded and fixed through anadhesive layer 55 onto the front surface (one principal surface) of thefront and rear surfaces (one principal surface and the other principalsurface opposing to each other) of the tab 54. A semiconductor chip 5has its rear surface bonded and fixed through an adhesive layer 55 ontothe rear surface (the other principal surface) of the front and rearsurfaces of the tab 54. Herein, the tab 54 is formed having a planarsize which is smaller than the planar size of each of the semiconductorchips (4, 5).

The semiconductor chips 4 and 5 are stacked in a state where the rearsurfaces of these semiconductor chips are faced to each other so thatone longer latus 4A1 of the semiconductor chip 4 and the other longerlatus 5A2 of the semiconductor chip 5 may confront the side of leads10A, and besides, where the positions of these semiconductor chips arestaggered relatively to each other so that one longer latus 4A1 of thesemiconductor chip 4 may lie outside the other longer latus 5A2 of thesemiconductor chip 5, as well as the side surface of the tab 54, andthat one longer latus 5A2 of the semiconductor chip 5 may lie outsidethe other longer latus 4A2 of the semiconductor chip 4, as well as theside surface of the tab 54 (that is, where the positions are relativelyshifted in the direction in which one longer latus 4A1 of thesemiconductor chip 4 and one longer latus 5A1 of the semiconductor chip5 come away from each other).

Owing to such a construction, in electrically connecting the electrodes6 of the semiconductor chip 4 with the inner portions of the leads 10Aby pieces of wire 11, a heat stage can be held in touch with the partialregion of the rear surface of the semiconductor chip 4 opposing to theelectrodes 6 thereof, and the heat of the heat stage is effectivelyconducted to the electrodes 6 of the semiconductor chip 4, so that theinferior connections between the electrodes 6 of the semiconductor chip4 and the wire pieces 11 can be relieved. Besides, in electricallyconnecting the electrodes 6 of the semiconductor chip 5 with the innerportions of leads 10B by pieces of wire 11, a heat stage can be held intouch with the partial region of the rear surface of the semiconductorchip 5 opposing to the electrodes 6 thereof, and the heat of the heatstage is effectively conducted to the electrodes 6 of the semiconductorchip 5, so that the inferior connections between the electrodes 6 of thesemiconductor chip 5 and the wire pieces 11 can be relieved. As aresult, the available percentage of products can be heightened also forthe semiconductor device 50 having the tab 54.

EMBODIMENT 12

FIG. 45 is a sectional view of a semiconductor device being Embodiment12 of the present invention.

As illustrated in FIG. 45, the semiconductor device 51 of thisembodiment has basically the same construction as that of Embodiment 11described above, but it differs from the foregoing embodiment inconstructional points explained below.

Semiconductor chips 4 and 5 are stacked in a state where the rearsurfaces of these semiconductor chips are faced to each other so thatone longer latus 4A1 of the semiconductor chip 4 and the other longerlatus 5A2 of the semiconductor chip 5 may confront the side of leads10A, and besides, where the positions of these semiconductor chips arestaggered relatively to each other so that the side surface y1 of a tab54 existing on the same side as one longer latus 4A1 of thesemiconductor chip 4 may lie outside the inner side end x1 of each ofthe electrodes 6 of the semiconductor chip 4 and that the side surfacey2 of the tab 54 existing on the same side as one longer latus 5A1 ofthe semiconductor chip 5 may lie outside the inner side end x2 of eachof the electrodes 6 of the semiconductor chip 5 (that is, where thepositions are relatively shifted in the direction in which one longerlatus 4A1 of the semiconductor chip 4 and one longer latus 5A1 of thesemiconductor chip 5 come near to each other).

Owing to such a construction, even when the planar size of the tab 54 ismade smaller than the planar size of each of the semiconductor chips (4,5) in order to reduce the area of each adhesive layer 55, the region ofthe rear surface of the semiconductor chip 4 opposing to the electrodes6 thereof and the region of the rear surface of the semiconductor chip 5opposing to the electrodes 6 thereof are supported by the tab 54.Therefore, bondability on the occasion of connecting one end side ofeach piece of wire 11 to the corresponding electrode 6 of thesemiconductor chip 4 is enhanced, and bondability on the occasion ofconnecting one end side of each piece of wire 11 to the correspondingelectrode 6 of the semiconductor chip 5 is enhanced.

EMBODIMENT 13

FIG. 46 is a sectional view of a semiconductor device being Embodiment13 of the present invention.

As illustrated in FIG. 46, the semiconductor device 52 of thisembodiment has basically the same construction as that of Embodiment 10described before, but it differs from the foregoing embodiment inconstructional points explained below.

The semiconductor device 52 is constructed having a tab 54. Asemiconductor chip 4 has its rear surface bonded and fixed through anadhesive layer 55 onto the front surface (one principal surface) of thefront and rear surfaces (one principal surface and the other principalsurface opposing to each other) of the tab 54. A semiconductor chip 5has its rear surface bonded and fixed through an adhesive layer 55 ontothe rear surface (the other principal surface) of the front and rearsurfaces of the tab 54. Herein, the tab 54 is formed having a planarsize which is larger than the planar size of each of the semiconductorchips (4, 5).

The semiconductor chips 4 and 5 are stacked in a state where the rearsurfaces of these semiconductor chips are faced to each other so thatone longer latus 4A1 of the semiconductor chip 4 and the other longerlatus 5A2 of the semiconductor chip 5 may confront the side of leads10A.

Pieces of wire 11 are connected by reverse bonding which connects eachwire piece on the side of the corresponding lead earlier (first bonding)and connects it on the side of the corresponding electrode of thesemiconductor chip later (second bonding). At the first bonding, inorder to prevent the wire piece required especially in ball bonding.Accordingly, the wire connection surface of each lead 10A is locatednearer to the side of the semiconductor chip 5 with respect to thecircuit forming surface 4A of the semiconductor chip 4, whereupon theconnection between the electrodes of the semiconductor chip 4 and thewire connection surface of the lead 10A by the wire piece 11 is done bythe reverse bonding. Thus, the pull-up of the wire piece 11 is cancelledby the level difference between the circuit forming surface 4A of thesemiconductor chip 4 and the wire connection surface of the lead 10A, sothat the resin thickness of a resin body 12 on the side of the circuitforming surface 4A of the semiconductor chip 4 can be reduced. Likewise,the wire connection surface of each lead 10B is located nearer to theside of the semiconductor chip 4 with respect to the circuit formingsurface 5A of the semiconductor chip 5, whereupon the connection betweenthe electrode 6 of the semiconductor chip 5 and the wire connectionsurface of the lead 10B by the wire piece 11 is done by the reversebonding. Thus, the pull-up of the wire piece 11 is cancelled by thelevel difference between the circuit forming surface 5A of thesemiconductor chip 5 and the wire connection surface of the lead 10B, sothat the resin thickness of the resin body 12 on the side of the circuitforming surface 5A of the semiconductor chip 5 can be reduced. As aresult, a thinned structure can be attained even in the semiconductordevice 52 having the tab 54.

By the way, salient electrodes may well be provided on the electrodes 6of the respective semiconductor chips 4, 5. In this case, theconnections of the wire pieces 11 at the second bonding are facilitated.

EMBODIMENT 14

In this embodiment, there will be described an example in which thepresent invention is applied to a semiconductor device wherein twosemiconductor chips each having a built-in DRAM (Dynamic Random AccessMemory) are encapsulated with an one resin body.

FIG. 47 is a sectional view of a semiconductor device being Embodiment14 of the present invention, while FIG. 48 is a plan view ofsemiconductor chips which are assembled in the semiconductor device.

As illustrated in FIG. 48, each of the semiconductor chips 4, 5 is soconstructed that a plurality of electrodes 6 are arranged in the stateof one column at the central part of its circuit forming surface (4A or5A) and in the direction of the longer latera thereof. In a case wheresuch semiconductor chips 4, 5 have been stacked with their rear surfacesfacing to each other, the stacked structure falls into a state where theelectrodes 6 of the same functions on the respective semiconductor chips4, 5 oppose in the vertical direction of this stacked structure. Asillustrated in FIG. 47, therefore, a single lead 10A arranged on theside of one longer latus of the semiconductor chip 4 and the electrodes6 of the identical function on the respective semiconductor chips 4, 5can be electrically connected by pieces of wire 11. Also, a single lead10B arranged on the side of the other longer latus of the semiconductorchip 4 and the electrodes 6 of the identical function on the respectivesemiconductor chips 4, 5 can be electrically connected by pieces of wire11.

In the semiconductor device 60 of this embodiment, the wire connectionsurface of each of the leads (10A, 10B) lies midway between the circuitforming surface 4A of the semiconductor chip 4 and the circuit formingsurface 5A of the semiconductor chip 5. Accordingly, the connectionsbetween the electrode 6 of the semiconductor chip 4 and the wireconnection surfaces (the upper sides as viewed in FIG. 47) of the leads(10A, 10B) by the wire pieces 11 are done by reverse bonding as in theforegoing embodiment 13, whereby the pull-up of the wire pieces 11 iscancelled by the level difference between the circuit forming surface 4Aof the semiconductor chip 4 and the wire connection surfaces of theleads 10A, so that the resin thickness of the resin body 12 on the sideof the circuit forming surface 4A of the semiconductor chip 4 can bereduced. Likewise, the connections between the electrode 6 of thesemiconductor chip 5 and the wire connection surfaces (the lower sidesas viewed in FIG. 47) of the leads (10A; 10B) by the wire pieces 11 aredone by the reverse bonding, whereby the pull-up of the wire pieces 11is cancelled by the level difference between the circuit forming surface5A of the semiconductor chip 5 and the wire connection surfaces of theleads 10B, so that the resin thickness of the resin body 12 on the sideof the circuit forming surface 5A of the semiconductor chip 5 can bereduced. As a result, it is permitted to thin the structure of thesemiconductor device 60 wherein the two semiconductor chips (4, 5) eachhaving the electrodes 6 arranged at the central part of its circuitforming surface are stacked and are encapsulated with the one resin body12.

By the way, although this embodiment has been described concerning thesemiconductor chips in each of which the electrodes 6 are arranged inthe state of one column at the central part of its circuit formingsurface, a thinned structure can be attained even with semiconductorchips in each of which electrodes 6 are arranged in the state of twozigzag columns at the central part of its circuit forming surface.

While the invention made by the inventors has been concretely describedabove in conjunction with the embodiments, it is a matter of course thatthe present invention is not restricted to the foregoing embodiments,but that it is variously alterable within a scope not departing from thepurport thereof.

By way of example, the present invention is applicable to semiconductordevices of SOJ (Small Outline J-leaded Package) type, SOP (Small OutlinePackage) type, etc. which have bidirectional lead array structures.

Besides, the present invention is applicable to semiconductor devices ofQFP (Quad Flatpack Package) type, QFJ (Quad Flatpack J-leaded Package)type, etc. which have quadridirectional lead array structures.

INDUSTRIAL APPLICABILITY

It is possible to thin the structure of a semiconductor device in whichtwo semiconductor chips are stacked and are encapsulated with an oneresin body.

Besides, it is possible to heighten the available percentage of theproducts of the semiconductor device.

What is claimed is:
 1. A semiconductor device, comprising: a resin body;a first semiconductor chip and a second semiconductor chip which liewithin said resin body, each of which is formed in a square shape whenviewed in plan, and each of which is formed with a plurality ofelectrodes on a side of a first latus of a front surface of front andrear surfaces thereof and along the first latus; a plurality of firstleads which extend inside and outside said resin body, which arearranged outside said first latus of said first semiconductor chip, andwhich are electrically connected to the corresponding electrodes of saidfirst semiconductor chip through pieces of conductive wire; a pluralityof second leads which extend inside and outside said resin body, whichare arranged outside a second latus of said first semiconductor chipopposing to said first latus thereof, and which are electricallyconnected to the corresponding electrodes of said second semiconductorchip through pieces of conductive wire; and supporting leads whichsupport said first semiconductor chip and said second semiconductorchip; wherein said first semiconductor chip and said secondsemiconductor chip are bonded and fixed to each other in a state wherethe rear surfaces of the respective semiconductor chips are faced toeach other so that the second latus of said first semiconductor chip andsaid first latus of said second semiconductor chip may confront a sideof said second leads; and said supporting leads are bonded and fixed toeither of the front surface of said first semiconductor chip or thefront surface of said second semiconductor chip.
 2. A semiconductordevice according to claim 1, wherein said first semiconductor chip andsaid second semiconductor chip are bonded and fixed in a state wherepositions of the respective semiconductor chips are staggered relativelyto each other so that said electrodes of said first semiconductor chipmay lie outside a second latus of said second semiconductor chipopposing to said first latus thereof, and that said electrodes of saidsecond semiconductor chip may lie outside said second latus of saidfirst semiconductor chip.
 3. A semiconductor device according to claim2, wherein said first semiconductor chip and said second semiconductorchip are bonded and fixed in a state where the positions of therespective semiconductor chips are staggered relatively to each other sothat a third latus of said first semiconductor chip intersecting withsaid first latus thereof may lie outside a third latus of said secondsemiconductor chip intersecting with said first latus thereof and lyingon the same side as the third latus of said first semiconductor chip,and that a fourth latus of said second semiconductor chip opposing tothe third latus thereof may lie outside a fourth latus of said firstsemiconductor chip opposing to said third latus thereof and lying on thesame side as the fourth latus of said second semiconductor chip.
 4. Asemiconductor device, comprising: a resin body; a first semiconductorchip and a second semiconductor chip which lie within said resin body,each of which is formed in a square shape when viewed in plan, and eachof which is formed with a plurality of electrodes on a side of a firstlatus of a front surface of front and rear surfaces thereof and alongthe first latus; a plurality of first leads which extend inside andoutside said resin body, which are arranged outside said first latus ofsaid first semiconductor chip, and which are electrically connected tothe corresponding electrodes of said first semiconductor chip throughpieces of conductive wire; a plurality of second leads which extendinside and outside said resin body, which are arranged outside a secondlatus of said first semiconductor chip opposing to said first latusthereof, and which are electrically connected to the correspondingelectrodes of said second semiconductor chip through pieces ofconductive wire; a first supporting lead which is arranged outside athird latus of said first semiconductor chip intersecting with saidfirst latus thereof and outside a third latus of said secondsemiconductor chip intersecting with said first latus thereof; and asecond supporting lead which is arranged outside a fourth latus of saidfirst semiconductor chip opposing to the third latus thereof and outsidea fourth latus of said second semiconductor chip opposing to the thirdlatus thereof; wherein said first semiconductor chip and said secondsemiconductor chip are bonded and fixed to each other in a state wherethe rear surfaces of the respective semiconductor chips are faced toeach other so that the second latus of said first semiconductor chip andsaid first latus of said second semiconductor chip may confront a sideof said second leads, and where positions of said respectivesemiconductor chips are staggered relatively to each other so that saidthird latus of said first semiconductor chip may lie outside said thirdlatus of said second semiconductor chip and that the fourth latus ofsaid second semiconductor chip may lie outside the fourth latus of saidfirst semiconductor chip; said first supporting lead is bonded and fixedonto the rear surface of said first semiconductor chip outside saidthird latus of said second semiconductor chip; and said secondsupporting lead is bonded and fixed onto the rear surface of said secondsemiconductor chip outside said fourth latus of said first semiconductorchip.
 5. A semiconductor device according to claim 4, wherein said firstsemiconductor chip and said second semiconductor chip are bonded andfixed in a state where the positions of said respective semiconductorchips are staggered relatively to each other so that said electrodes ofsaid first semiconductor chip may lie outside a second latus of saidsecond semiconductor chip opposing to said first latus thereof, and thatsaid electrodes of said second semiconductor chip may lie outside saidsecond latus of said first semiconductor chip.
 6. A semiconductordevice, comprising: a resin body; a first semiconductor chip and asecond semiconductor chip which lie within said resin body, each ofwhich is formed in a square shape when viewed in plan, and each of whichis formed with a plurality of electrodes on a side of a first latus of afront surface of front and rear surfaces thereof and along the firstlatus; a plurality of first leads which extend inside and outside saidresin body, which are arranged outside said first latus of said firstsemiconductor chip, and which are electrically connected to thecorresponding electrodes of said first semiconductor chip through piecesof conductive wire; a plurality of second leads which extend inside andoutside said resin body, which are arranged outside a second latus ofsaid first semiconductor chip opposing to said first latus thereof, andwhich are electrically connected to the corresponding electrodes of saidsecond semiconductor chip through pieces of conductive wire; a firstsupporting lead which is arranged outside a third latus of said firstsemiconductor chip intersecting with said first latus thereof andoutside a third latus of said second semiconductor chip intersectingwith said first latus thereof; and a second supporting lead which isarranged outside a fourth latus of said first semiconductor chipopposing to the third latus thereof and outside a fourth latus of saidsecond semiconductor chip opposing to the third latus thereof; whereinsaid first semiconductor chip and said second semiconductor chip arebonded and fixed to each other in a state where the rear surfaces of therespective semiconductor chips are faced to each other so that thesecond latus of said first semiconductor chip and said first latus ofsaid second semiconductor chip may confront a side of said second leads;said first supporting lead is bonded and fixed onto the front surface ofsaid first semiconductor chip and on a side of said third latus thereof;and said second supporting lead is bonded and fixed onto the frontsurface of said second semiconductor chip and on a side of the fourthlatus thereof.
 7. A semiconductor device according to claim 6, whereinsaid first semiconductor chip and said second semiconductor chip arebonded and fixed in a state where positions of said respectivesemiconductor chips are staggered relatively to each other so that saidelectrodes of said first semiconductor chip may lie outside a secondlatus of said second semiconductor chip opposing to said first latusthereof, and that said electrodes of said second semiconductor chip maylie outside said second latus of said first semiconductor chip.
 8. Asemiconductor device according to claim 7, wherein said firstsemiconductor chip and said second semiconductor chip are bonded andfixed in a state where the positions of said respective semiconductorchips are staggered relatively to each other so that said third latus ofsaid first semiconductor chip may lie outside said third latus of saidsecond semiconductor chip, and that said fourth latus of said secondsemiconductor chip may lie outside the fourth latus of said firstsemiconductor chip.
 9. A semiconductor device, comprising: a resin body;a first semiconductor chip and a second semiconductor chip which liewithin said resin body, each of which is formed in a square shape whenviewed in plan, and each of which is formed with a plurality ofelectrodes on a side of a first latus of a front surface of front andrear surfaces thereof and along the first latus; a plurality of firstleads which extend inside and outside said resin body, which arearranged on the side of said first latus of said first semiconductorchip, and which are electrically connected to the correspondingelectrodes of said first semiconductor chip through pieces of conductivewire; and a plurality of second leads which extend inside and outsidesaid resin body, which are arranged on a side of a second latus of saidfirst semiconductor chip opposing to said first latus thereof, and whichare electrically connected to the corresponding electrodes of saidsecond semiconductor chip through pieces of conductive wire; whereinsaid first semiconductor chip and said second semiconductor chip arestacked in a state where the rear surfaces of the respectivesemiconductor chips are faced to each other so that said first latus ofsaid first semiconductor chip and a second latus of said secondsemiconductor chip opposing to said first latus thereof may confront aside of said first leads, and where positions of said respectivesemiconductor chips are staggered relatively to each other so that thesecond latus of said first semiconductor chip may lie outside said firstlatus of said second semiconductor chip and that the second latus ofsaid second semiconductor chip may lie outside said first latus of saidfirst semiconductor chip; each of said plurality of first leads has adistal end part of its inner portion, which lies within said resin body,bonded and fixed onto the rear surface of said second semiconductor chipoutside said first latus of said first semiconductor chip; and each ofsaid plurality of second leads has a distal end part of its innerportion, which lies within said resin body, bonded and fixed onto therear surface of said first semiconductor chip outside said first latusof said second semiconductor chip.
 10. A semiconductor device accordingto claim 9, wherein said rear surfaces of said first semiconductor chipand said second semiconductor chip are held in touch with each other.11. A semiconductor device according to claim 9, wherein said rearsurfaces of each first semiconductor chip and said second semiconductorchip are bonded and fixed to each other through an adhesive layer.
 12. Asemiconductor device according to claim 9, wherein: those wireconnection surfaces of said first leads to which the wire pieces areconnected lie nearer to a side of said second semiconductor chip withrespect to the front surface of said first semiconductor chip; and thosewire connection surfaces of said second leads to which the wire piecesare connected lie nearer to a side of said first semiconductor chip withrespect to the front surface of said second semiconductor chip.
 13. Asemiconductor device according to claim 9, wherein: said inner portionof each of said first leads is constructed having a first part whichtraverses a latus of said real surface of said second semiconductor chipand which is bonded and fixed to said rear surface of said secondsemiconductor chip, a second part which bends from said first parttoward a side of the front surface of said first semiconductor chip, anda third part which extends from said second part in the same directionas that of said first part; and said inner portion of each of saidsecond leads is constructed having a first part which traverses a latusof said rear surface of said first semiconductor chip and which is fixedto said rear surface of said first semiconductor chip, a second partwhich bends from said first part of said inner portion of said eachsecond lead toward the side of said front surface of said firstsemiconductor chip, and a third part which extends from said second partof said inner portion of said each second lead in the same direction asthat of said first part of said inner portion of said each second lead.14. A semiconductor device, comprising: a resin body; a firstsemiconductor chip and a second semiconductor chip which lie within saidresin body, each of which is formed in a square shape when viewed inplan, and each of which is formed with a plurality of electrodes on aside of a first latus of a front surface of front and rear surfacesthereof and along the first latus; a plurality of first leads whichextend inside and outside said resin body, which are arranged on theside of said first latus of said first semiconductor chip, and which areelectrically connected to the corresponding electrodes of said firstsemiconductor chip through pieces of conductive wire; and a plurality ofsecond leads which extend inside and outside said resin body, which arearranged on a side of a second latus of said first semiconductor chipopposing to said first latus thereof, and which are electricallyconnected to the corresponding electrodes of said second semiconductorchip through pieces of conductive wire; wherein said first semiconductorchip and said second semiconductor chip are stacked in a state where therear surfaces of the respective semiconductor chips are faced to eachother so that said first latus of said first semiconductor chip and asecond latus of said second semiconductor chip opposing to said firstlatus thereof may confront a side of said first leads, and wherepositions of said respective semiconductor chips are staggeredrelatively to each other so that said first latus of said firstsemiconductor chip may lie outside the second latus of said secondsemiconductor chip and that said first latus of said secondsemiconductor chip may lie outside the second latus of said firstsemiconductor chip; each of said plurality of first leads has a distalend part of its inner portion, which lies within said resin body, bondedand fixed onto the rear surface of said first semiconductor chip outsidesaid second latus of said second semiconductor chip; and each of saidplurality of second leads has a distal end part of its inner portion,which lies within said resin body, bonded and fixed onto the rearsurface of said second semiconductor chip outside said second latus ofsaid first semiconductor chip.
 15. A semiconductor device according toclaim 14, wherein: said inner portion of each of said first leads isconstructed having a first part which traverses a laths of said rearsurface of said first semiconductor chip and which is bonded and fixedto said rear surface of said first semiconductor chip, a second partwhich bends from said first part toward a side of the front surface ofsaid first semiconductor chip, and a third part which extends from saidsecond part in the same direction as that of said first part; and saidinner portion of each of said second leads is constructed having a firstpart which traverses a latus of said rear surface of said secondsemiconductor chip and which is fixed to said rear surface of saidsecond semiconductor chip, a second part which bends from said firstpart of said inner portion of said each second lead toward the side ofsaid front surface of said first semiconductor chip, and a third partwhich extends from said second part of said inner portion of said eachsecond lead in the same direction as that of said first part of saidinner portion of said each second lead.
 16. A semiconductor device,comprising: a resin body; a first semiconductor chip and a secondsemiconductor chip which lie within said resin body, each of which isformed in a square shape when viewed in plan, and each of which isformed with a plurality of electrodes on a side of a first latus of afront surface of front and rear surfaces thereof and along the firstlatus; a plurality of first leads which extend inside and outside saidresin body, which are arranged on the side of said first latus of saidfirst semiconductor chip, and which are electrically connected to thecorresponding electrodes of said first semiconductor chip through piecesof conductive wire; and a plurality of second leads which extend insideand outside said resin body, which are arranged on a side of a secondlatus of said first semiconductor chip opposing to said first latusthereof, and which are electrically connected to the correspondingelectrodes of said second semiconductor chip through pieces ofconductive wire; wherein said first semiconductor chip and said secondsemiconductor chip are stacked in a state where the rear surfaces of therespective semiconductor chips are faced to each other so that saidfirst latus of said first semiconductor chip and a second latus of saidsecond semiconductor chip opposing to said first latus thereof mayconfront a side of said first leads, and where positions of saidrespective semiconductor chips are staggered relatively to each other sothat the second latus of said first semiconductor chip may lie outsidesaid first latus of said second semiconductor chip and that the secondlatus of said second semiconductor chip may lie outside said first latusof said first semiconductor chip; each of said plurality of first leadshas a distal end part of its inner portion, which lies within said resinbody, bonded and fixed onto the rear surface of said secondsemiconductor chip outside said first latus of said first semiconductorchip; and each of said plurality of second leads has a distal end partof its inner portion, which lies within said resin body, bonded andfixed onto the front surface of said first semiconductor chip and on theside of said second latus of said first semiconductor chip.
 17. Asemiconductor device according to claim 16, wherein: said inner portionof each of said first leads is constructed having a first part whichtraverses a latus of said rear surface of said second semiconductor chipand which is bonded and fixed to said rear surface of said secondsemiconductor chip, a second part which bends from said first parttoward a side of said front surface of said first semiconductor chip,and a third part which extends from said second part in the samedirection as that of said first part; and said inner portion of each ofsaid second leads is constructed having a first part which traversessaid second latus of said first semiconductor chip and which is bondedand fixed to said front surface of said first semiconductor chip, asecond part which bends from said first part of said inner portion ofsaid each second lead toward a side of the rear surface of said firstsemiconductor chip, and a third part which extends from said second partof said inner portion of said each second lead in the same direction asthat of said first part of said inner portion of said each second lead.18. A semiconductor device, comprising: a resin body; a firstsemiconductor chip and a second semiconductor chip which lie within saidresin body, each of which is formed in a square shape when viewed inplan, and each of which is formed with a plurality of electrodes on aside of a first latus of a front surface of front and rear surfacesthereof and along the first latus; a plurality of first leads whichextend inside and outside said resin body, which are arranged on theside of said first latus of said first semiconductor chip, and which areelectrically connected to the corresponding electrodes of said firstsemiconductor chip through pieces of conductive wire; and a plurality ofsecond leads which extend inside and outside said resin body, which arearranged on a side of a second latus of said first semiconductor chipopposing to said first latus thereof, and which are electricallyconnected to the corresponding electrodes of said second semiconductorchip through pieces of conductive wire; wherein said first semiconductorchip and said second semiconductor chip are stacked in a state where therear surface of said first semiconductor chip and the front surface ofsaid second semiconductor chip are faced to each other so that saidfirst latus of said first semiconductor chip and a second latus of saidsecond semiconductor chip opposing to said first latus thereof mayconfront a side of said first leads, and where positions of therespective semiconductor chips are staggered relatively to each other sothat said first latus of said first semiconductor chip may lie outsidethe second latus of said second semiconductor chip and that said firstlatus of said second semiconductor chip may lie outside the second latusof said second semiconductor chip; each of said plurality of first leadshas a distal end part of its inner portion, which lies within said resinbody, bonded and fixed onto said rear surface of said firstsemiconductor chip outside said second latus of said first semiconductorchip; and each of said plurality of second leads has a distal end partof its inner portion, which lies within said resin body, bonded andfixed onto the rear surface of said second semiconductor chip on a sideof said first latus of said second semiconductor chip.
 19. Asemiconductor device according to claim 18, wherein said rear surface ofsaid first semiconductor chip and said front surface of said secondsemiconductor chip are held in touch with each other.
 20. Asemiconductor device according to claim 18, wherein said rear surface ofsaid first semiconductor chip and said front surface of said secondsemiconductor chip are bonded and fixed to each other through anadhesive layer.
 21. A semiconductor device according to claim 18,wherein: said inner portion of each of said first leads is constructedhaving a first part which traverses a latus of said rear surface of saidfirst semiconductor chip and which is bonded and fixed to said rearsurface of said first semiconductor chip, a second part which bends fromsaid first part toward a side of the front surface of said firstsemiconductor chip, and a third part which extends from said second partin the same direction as that of said first part; and said inner portionof each of said second leads is constructed having a first part whichtraverses a latus of said rear surface of said second semiconductor chipand which is fixed to said rear surface of said second semiconductorchip, a second part which bends from said first part of said innerportion of said each second lead toward the side of said front surfaceof said first semiconductor chip, and a third part which extends fromsaid second part of said inner portion of said each second lead in thesame direction as that of said first part of said inner portion of saideach second lead.
 22. A semiconductor device, comprising: a resin body;a first semiconductor chip and a second semiconductor chip which liewithin said resin body, each of which is formed in a square shape whenviewed in plan, and each of which is formed with a plurality ofelectrodes on a side of a first latus of a front surface of front andrear surfaces thereof and along the first latus; a plurality of firstleads which extend inside and outside said resin body, which arearranged on the side of said first latus of said first semiconductorchip, and which are electrically connected to the correspondingelectrodes of said first semiconductor chip through pieces of conductivewire; a plurality of second leads which extend inside and outside saidresin body, which are arranged on a side of a second latus of said firstsemiconductor chip opposing to said first latus thereof, and which areelectrically connected to the corresponding electrodes of said secondsemiconductor chip through pieces of conductive wire; a first supportinglead which supports said first semiconductor chip; and a secondsupporting lead which supports said second semiconductor chip; whereinsaid first semiconductor chip and said second semiconductor chip arestacked in a state where the rear surfaces of the respectivesemiconductor chips are faced to each other so that said first latus ofsaid first semiconductor chip and a second latus of said secondsemiconductor chip opposing to said first latus thereof may confront aside of said first leads, and where positions of said respectivesemiconductor chips are staggered relatively to each other so that thesecond latus of said first semiconductor chip may lie outside said firstlatus of said second semiconductor chip and that the second latus ofsaid second semiconductor chip may lie outside said first latus of saidfirst semiconductor chip; said first supporting lead is bonded and fixedonto the rear surface of said first semiconductor chip and outside saidfirst latus of said second semiconductor chip; and said secondsupporting lead is bonded and fixed onto the rear surface of said secondsemiconductor chip outside said first latus of said first semiconductorchip.
 23. A semiconductor device according to claim 22, wherein saidrear surfaces of said first semiconductor chip or said secondsemiconductor chip are held in touch with each other.
 24. Asemiconductor device according to claim 22, wherein said rear surfacesof said first semiconductor chip and said second semiconductor chip arebonded and fixed to each other through an adhesive layer.
 25. Asemiconductor device, comprising: a resin body; a first semiconductorchip and a second semiconductor chip which lie within said resin body,each of which is formed in a square shape when viewed in plan, and eachof which is formed with a plurality of electrodes on a side of a firstlatus of a front surface of front and rear surfaces thereof and alongthe first latus; a plurality of first leads which extend inside andoutside said resin body, which are arranged on the side of said firstlatus of said first semiconductor chip, and which are electricallyconnected to the corresponding electrodes of said first semiconductorchip through pieces of conductive wire; a plurality of second leadswhich extend inside and outside said resin body, which are arranged on aside of a second latus of said first semiconductor chip opposing to saidfirst latus thereof, and which are electrically connected to thecorresponding electrodes of said second semiconductor chip throughpieces of conductive wire; a first supporting lead which supports saidfirst semiconductor chip; and a second supporting lead which supportssaid second semiconductor chip; wherein said first semiconductor chipand said second semiconductor chip are stacked in a state where the rearsurfaces of the respective semiconductor chips are faced to each otherso that said first latus of said first semiconductor chip and a secondlatus of said second semiconductor chip opposing to said first latusthereof may confront a side of said first leads, and where positions ofsaid respective semiconductor chips are staggered relatively to eachother so that said first latus of said first semiconductor chip may lieoutside the second latus of said second semiconductor chip and that saidfirst latus of said second semiconductor chip may lie outside saidsecond latus of said first semiconductor chip; said first supportinglead is bonded and fixed onto the front surface of said firstsemiconductor chip; and said second supporting lead is bonded and fixedonto the front surface of said second semiconductor chip.
 26. Asemiconductor device, comprising: a resin body; a first semiconductorchip and a second semiconductor chip which lie within said resin body,each of which is formed in a square shape when viewed in plan, and eachof which is formed with a plurality of electrodes on a side of a firstlatus of a front surface of front and rear surfaces thereof and alongthe first latus; a plurality of first leads which extend inside andoutside said resin body, which are arranged on the side of said firstlatus of said first semiconductor chip, and which are electricallyconnected to the corresponding electrodes of said first semiconductorchip through pieces of conductive wire; a plurality of second leadswhich extend inside and outside said resin body, which are arranged on aside of a second latus of said first semiconductor chip opposing to saidfirst latus thereof, and which are electrically connected to thecorresponding electrodes of said second semiconductor chip throughpieces of conductive wire; and a tab which has the rear surface of saidfirst semiconductor chip bonded and fixed onto a front surface of frontand rear surfaces thereof, and which has the rear surface of said secondsemiconductor chip bonded and fixed onto the rear surface of said frontand rear surfaces thereof; wherein said first semiconductor chip andsaid second semiconductor chip are stacked in a state where the rearsurfaces of the respective semiconductor chips are faced to each otherso that said first latus of said first semiconductor chip and a secondlatus of said second semiconductor chip opposing to said first latusthereof may confront a side of said first leads, and where positions ofsaid respective semiconductor chips are staggered relatively to eachother so that said first latus of said first semiconductor chip may lieoutside the second latus of said second semiconductor chip, as well as aside surface of said tab, and that said first latus of said secondsemiconductor chip may lie outside said second latus of said firstsemiconductor chip, as well as another side surface of said tab.
 27. Asemiconductor device, comprising: a resin body; a first semiconductorchip and a second semiconductor chip which lie within said resin body,each of which is formed in a square shape when viewed in plan, and eachof which is formed with a plurality of electrodes on a side of a firstlatus of a front surface of front and rear surfaces thereof and alongthe first latus; a plurality of first leads which extend inside andoutside said resin body, which are arranged on the side of said firstlatus of said first semiconductor chip, and which are electricallyconnected to the corresponding electrodes of said first semiconductorchip through pieces of conductive wire; a plurality of second leadswhich extend inside and outside said resin body, which are arranged on aside of a second latus of said first semiconductor chip opposing to saidfirst latus thereof, and which are electrically connected to thecorresponding electrodes of said second semiconductor chip throughpieces of conductive wire; and a tab which has the rear surface of saidfirst semiconductor chip bonded and fixed onto a front surface of frontand rear surfaces thereof, and which has the rear surface of said secondsemiconductor chip bonded and fixed onto the rear surface of said frontand rear surfaces thereof; wherein said first semiconductor chip andsaid second semiconductor chip are stacked in a state where the rearsurfaces of the respective semiconductor chips are faced to each otherso that said first latus of said first semiconductor chip and a secondlatus of said second semiconductor chip opposing to said first latusthereof may confront a side of said first leads, and where positions ofsaid respective semiconductor chips are staggered relatively to eachother so that a side surface of said tab on the same side as said firstlatus of said first semiconductor chip may lie outside inner side endsof said electrodes of said first semiconductor chip and that a sidesurface of said tab on the same side as said first latus of said secondsemiconductor chip may lie outside inner side ends of said electrodes ofsaid second semiconductor chip.
 28. A semiconductor device, comprising:a resin body; a first semiconductor chip and a second semiconductor chipwhich lie within said resin body, each of which is formed in a squareshape when viewed in plan, and each of which is formed with a pluralityof electrodes on a side of a first latus of a front surface of front andrear surfaces thereof and along the first latus; a plurality of firstleads which extend inside and outside said resin body, which arearranged on the side of said first latus of said first semiconductorchip, and which are electrically connected to the correspondingelectrodes of said first semiconductor chip through pieces of firstconductive wire; a plurality of second leads which extend inside andoutside said resin body, which are arranged on a side of a second latusof said first semiconductor chip opposing to said first latus thereof,and which are electrically connected to the corresponding electrodes ofsaid second semiconductor chip through pieces of second conductive wire;and a tab which has the rear surface of said first semiconductor chipbonded and fixed onto a front surface of front and rear surfacesthereof, and which has the rear surface of said second semiconductorchip bonded and fixed onto the rear surface of said front and rearsurfaces thereof; wherein wire connection surfaces of said first leadslie nearer to a side of said second semiconductor chip with respect tothe front surface of said first semiconductor chip; wire connectionsurfaces of said second leads lie nearer to a side of said firstsemiconductor chip with respect to the front surface of said secondsemiconductor chip; each of the first wire pieces is connected byreverse bonding in which it is bonded onto the wire connection surfaceof the corresponding first lead as first bonding and is subsequentlybonded to the corresponding electrode of said first semiconductor chipas second bonding; and each of the second wire pieces is connected byreverse bonding in which it is bonded onto the wire connection surfaceof the corresponding second lead as first bonding and is subsequentlybonded to the corresponding electrode of said second semiconductor chipas second bonding.